ICS932S208 datasheet(14/22 Pages) RENESAS

14 / 22 page

IDT® Programmable Timing Control HubTM for Next Gen P4TM Processor

0743H—03/15/13

ICS932S208

Programmable Timing Control HubTM for Next Gen P4TM Processor

2C Table: Output Control and Fix Frequency Register

Pin #

Name

Control Function

Type0

PWD

Bit 7

Test Clock Mode

Disable

Enable

Bit 6

RESERVED

Bit 5

FS Testmode

FS_A and FS_B

Operation

Normal

Test Mode

Bit 4

SRC100#

SRC Frequency

Select

100MHz

200MHz

Bit 3

RESERVED

Bit 2

SSEN

Spread Spectrum

Enable

Spread

OFF

Spread

Bit 1

REF1

Output Control

Disable

Enable

Bit 0

REF0

Output Control

Disable

Enable

2C Table: Vendor & Revision ID Register

Pin #

Name

Control Function

Type0

PWD

Bit 7

RID3

Bit 6

RID2

Bit 5

RID1

Bit 4

RID0

Bit 3

VID3

Bit 2

VID2

Bit 1

VID1

Bit 0

VID0

VENDOR ID

Byte 7

REVISION ID

37,38

7,8,9,12,13,14,15,1

8,19,20,22,23,26,27

,29,31,32,37,38,40,

41,43,44,46,47

40,41,43,44,46,47

1,2,7,8,9,12,13,14,

15,18,19,20,22,23,2

6,27,29,31,32,37,38

,40,41,43,44,46,47

Byte 6

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