PC2119RUSLASH2 datasheet(38/60 Pages) PHILIPS

38 / 60 page

28. August 2000

Philips Semiconductors

Product speciﬁcation

LCD controllers/drivers

PCF2119x-2

14 AC CHARACTERISTICS

VDD1 = 1.5 to 5.5 V; VDD2,3 = 2.2 to 4.0 V; VSS =0V; VLCD = 2.2 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise speciﬁed.

Note

All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with

an input voltage swing of VSS to VDD.

CB = total capacitance of one bus line in pF.

3. Tested on a sample basis.

SYMBOL

PARAMETER

CONDITIONS

MIN.

TYP.

MAX.

UNIT

fFR

LCD frame frequency (internal clock)

VDD = 5.0 V

147

fOSC

oscillator frequency (not available at any pad)

140

250

450

kHz

fOSC(ext)

external clock frequency

140

−

450

kHz

tOSCST

oscillator start-up time after power-down

note 3

−

200

300

µs

tW(R,PD)

reset and power down high level pulse width

tSW(R,PD)

tolerable spike width on PD and Reset pads

Bus timing characteristics: parallel interface; note 1

WRITE OPERATION (WRITING DATA FROM MPU TO PCF2119X)

Tcy(en)

enable cycle time

500

−−

tW(en)

enable pulse width

220

−−

tsu(A)

address set-up time

−−

th(A)

address hold time

−−

tsu(D)

data set-up time

−−

th(D)

data hold time

−−

READ OPERATION (READING DATA FROM PCF2119XTO MPU)

Tcy(en)

enable cycle time

500

−−

tW(en)

enable pulse width

220

−−

tsu(A)

address set-up time

−−

th(A)

address hold time

−−

td(D)

data delay time

VDD1 > 2.2 V

−−

150

VDD1 > 1.5 V

−−

250

th(D)

data hold time

−

100

Timing characteristics: I2C-bus interface; note 1

fSCL

SCL clock frequency

−−

400

kHz

tLOW

SCL clock low period

1.3

−−µs

tHIGH

SCL clock high period

0.6

−−µs

tSU;DAT

data set-up time

100

−−

tHD;DAT

data hold time

−−

SCL, SDA rise time

note 2, 3

15 + 0.1 CB

−

300

SCL, SDA fall time

note 2, 3

15 + 0.1 CB

−

300

capacitive bus line load

−−

400

tSU;STA

set-up time for a repeated START condition

0.6

−−µs

tHD;STA

START condition hold time

0.6

−−µs

tSU;STO

set-up time for STOP condition

0.6

−−µs

tSW

tolerable spike width on bus

−−

tBUF

Bus free time between STOP and START condition

1.3

PC2119RU/2 Datasheet(PDF) 38 Page - NXP Semiconductors

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