ICS9248-99

General Description

Power Groups

The ICS9248-99 is the single chip clock solutionfor Desktop

designs using 810/ 810/E style chipset. It provides all

necessary clock signals for such a system.

Spreadspectrummay be enabled through 12C programming.

Spread spectrum typically reduces systemEMI by 8dB to

10dB. This simplifiesEMI qualification without resorting to

board design iterations or costly shielding. The ICS9248-

99

GNDREF, VDDREF = REF1, X1, X2

GNDPCI, VDDPCI = PCICLK [7:0]

GNDSDR, VDDSDR = SDR AM [8:0]

GNDCOR, VDDCOR = supply for PLL core

GND3V66, VDD3V66 = 3V66

VDD48 = 48MHz, 24 48MHz,

VDDLAPIC = IOAPIC

GNDLCPU, VDDLCPU = CPUCLK [1 :OJ

employs a proprietary closed loop design, which tightly

controls the percentage of spreading over process and

temperature variations.

Serial programming 12C interface allows changing functions,

stop clock programming and frequency selection.

Pin Configuration

PIN NUMBER

PIN NAME

TYPE

DESCRIPTION

1

REFI

OUT

14.318 MHz reference clock.

FS3

IN

Frequency select pin.

2,6,16, 24,27,34,

VDD

PWR

3.3V Power supply for SDRAM output buffers,PCI output buffers,

42

reference outout buffers and 48MHz outout

3

XI

IN

Crystal input,nominally 14.318MHz.

4

X2

OUT

Crystal output,nominally 14.318MHz.

5,9,13,20,26,30,

GND

PWR

Ground pin for 3V outputs.

38

8,7

3V66 [1:0]

OUT

3.3V clock outputs

10

FS0

IN

Frequency select pin.

PCICLK0

OUT

PCI clock outout.

11

FSI

IN

Frequency select pin.

PCICLKI

OUT

PCI clock output.

12

FS2

IN

Frequency select pin.

PCICLK2

OUT

PCI clock output.

19,18,17,15,14

PCICLK [7:3]

OUT

PCI clock outputs.

21,22

48MHz

OUT

48MHz output clocks

SEL24 48#

IN

Select pin for enabling 24MHz or 48MHz

23

H=24MHz L=48MHz

24 48MHz

OUT

Clock output for super 1/O/USB

25

SDATA

IN

Data input for l2C serial input,5V tolerant input

28

SCLK

IN

Clock input ofl2C input,5V tolerant input

Asynchronous active low input pin used to power down the device into a low

29

PD#

IN

power state. The internal clocks are disabled and the VCO and the crystal are

stopped. The latency ofthe power down will not be greater than 3ms.

31,32,33,35,36, SDRAM [8:0]

OUT

SDRAM clock outputs

37 39.40 41

43

GNDLCPU

PWR

Ground pin for the CPU clocks.

44,45

CPUCLK [1:0]

OUT

CPU clock outputs.

46

VDDLCPU

PWR

Power pin for the CPUCLKs. 2.5V

47

IOAPIC

OUT

2.5V clock output.

48

VDDLAPIC

PWR

Power oin for the IOAPIC. 2.5V

0314C-----09/18/03

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