STC12LE5612 datasheet(39/377 Pages) STC

39 / 377 page

2.2.1 Slow Down Mode

A divider is designed to slow down the clock source prior to route to all logic circuit. The operating frequency of

internal logic circuit can therefore be slowed down dynamically , and then save the power.

User can slow down the MCU by means of writing a non-zero value to the CLKS[2:0] bits in the CLK_DIV

CLKS[2:0] to a non-zero value before entering the idle mode.

CLK_DIV register (Clock Divider)

SFR Name SFR Address

bit

CLK_DIV

C7H

name

CLKS2 CLKS1 CLKS0

B2-B0 (CLKS2-CLKS0) :

000 External crystal/clock or On-Chip R/C clock is not divided (default state)

001 External crystal/clock or On-Chip R/C clock is divided by 2.

010 External crystal/clock or On-Chip R/C clock is divided by 4.

011 External crystal/clock or On-Chip R/C clock is divided by 8.

100 External crystal/clock or On-Chip R/C clock is divided by 16.

101 External crystal/clock or On-Chip R/C clock is divided by 32.

110 External crystal/clock or On-Chip R/C clock is divided by 64.

111 External crystal/clock or On-Chip R/C clock is divided by 128.

Not-divided

÷2

÷4

÷8

÷16

÷32

÷64

÷128

CLKS2,CLKS1,CLKS0

000

001

010

011

100

101

110

111

System Clock

(To CPU and peripherals)

Clock Structure

On-Chip R/C Clock

External crystal/clock

STC12LE5612 Datasheet(PDF) 39 Page - STCmicro Technology Co,.Ltd

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