STC12LE5624 datasheet(40/377 Pages) STC

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2.2.2 Idle Mode

An instruction that sets IDL/PCON.0 causes that to be the last instruction executed before going into the idle

mode, the internal clock is gated off to the CPU but not to the interrupt, timer, PCA, ADC, SPI, WDT and serial

port functions. The PCA can be programmed either to pause or continue operating during Idle. The CPU status is

preserved in its entirety: the RAM, Stack Pointer, Program Counter, Program Status Word, Accumulator, and all

other registers maintain their data during Idle. The port pins hold the logical states they had at the time Idle was

activated. Idle mode leaves the peripherals running in order to allow them to wake up the CPU when an interrupt

is generated. Timer 0, Timer 1, PWM timer and UART will continue to function during Idle mode.

There are two ways to terminate the idle. Activation of any enabled interrupt will cause IDL/PCON.0 to be

cleared by hardware, terminating the idle mode. The interrupt will be serviced, and following RETI, the next

instruction to be executed will be the one following the instruction that put the device into idle.

The flag bits (GF0 and GF1) can be used to give art indication if an interrupt occurred during normal operation

or during Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is

terminated by an interrupt, the interrupt service routine can examine the flag bits.

The other way to wake-up from idle is to pull RESET high to generate internal hardware reset.Since the clock

oscillator is still running, the hardware reset neeeds to be held active for only two machine cycles(24 oscillator

periods) to complete the reset.

STC12LE5624 Datasheet(PDF) 40 Page - STCmicro Technology Co,.Ltd