NAND04GW3B2B datasheet(7/58 Pages) STMICROELECTRONICS

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NAND04GW3B2B, NAND08GW3B2A

Summary description

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Summary description

The NAND Flash 2112 Byte/ 1056 Word Page is a family of non-volatile Flash memories

that uses NAND cell technology. The NAND04GW3B2B and NAND08GW3B2A have a

density of 4 Gbits and 8 Gbits, respectively. They operate from a 3V voltage supply. The size

of a Page is 2112 Bytes (2048 + 64 spare).

The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8

Input/Output bus. This interface reduces the pin count and makes it possible to migrate to

other densities without changing the footprint.

Each block can be programmed and erased over 100,000 cycles. To extend the lifetime of

NAND Flash devices it is strongly recommended to implement an Error Correction Code

(ECC).

The device has hardware and software security features:

●

A Write Protect pin is available to give a hardware protection against program and

erase operations.

●

A Block Locking scheme is available to provide user code and/or data protection.

The device features an open-drain Ready/Busy output that can be used to identify if the

Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output

allows the Ready/Busy pins from several memories to be connected to a single pull-up

resistor.

A Copy Back Program command is available to optimize the management of defective

blocks. When a Page Program operation fails, the data can be programmed in another page

without having to resend the data to be programmed.

The NAND04GW3B2B and NAND08GW3B2A have Cache Program and Cache Read

features which improve the program and read throughputs for large files. During Cache

Programming, the device loads the data in a Cache Register while the previous data is

transferred to the Page Buffer and programmed into the memory array. During Cache

Reading, the device loads the data in a Cache Register while the previous data is

transferred to the I/O Buffers to be read.

The device has the Chip Enable Don’t Care feature, which allows code to be directly

downloaded by a microcontroller, as Chip Enable transitions during the latency time do not

stop the read operation.

The devices have the option of a Unique Identifier (serial number), which allows each device

to be uniquely identified.

The Unique Identifier options is subject to an NDA (Non Disclosure Agreement) and so not

described in the datasheet. For more details of this option contact your nearest ST Sales

office.

The device is available in a TSOP48 (12 x 20mm) package. In order to meet environmental

requirements, ST offers the NAND04GW3B2B and NAND08GW3B2A in ECOPACK®

package. ECOPACK packages are Lead-free. The category of second Level Interconnect is

marked on the package and on the inner box label, in compliance with JEDEC Standard

JESD97. The maximum ratings related to soldering conditions are also marked on the inner

box label. ECOPACK is an ST trademark.

NAND04GW3B2B Datasheet(PDF) 7 Page - STMicroelectronics

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