17

Integrated

Circuit

Systems, Inc.

ICS950202

0461M—02/10/06

All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no

defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard skew

described below as Tpci.

3V66 & PCI Phase Relationship

3V66 (1:0)

3V66 (4:2)

3V66_5

PCICLK_F (2:0) PCICLK (6:0)

Tpci

PD# Functionality

#

P

O

T

S

_

U

P

CT

U

P

CC

U

P

C6

6

V

3T

U

O

_

z

H

M

6

6

F

_

K

L

C

I

C

P

K

L

C

I

C

P

K

L

C

I

C

P

T

O

D

/

B

S

U

z

H

M

8

4

1l

a

m

r

o

Nl

a

m

r

o

Nz

H

M

6

6N

I

_

z

H

M

6

6N

I

_

z

H

M

6

6N

I

_

z

H

M

6

6z

H

M

8

4

0t

l

u

M

*

f

e

r

it

a

o

l

Fw

o

Lw

o

Lw

o

Lw

o

Lw

o

L

Group Skews at Common Transition Edges

GROUP

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

3V66

3V66

3V66 (5:0) pin to pin skew

0

500

ps

PCI

PCI

PCI_F (2:0) and PCI (6:0) pin to pin skew

0

500

ps

3V66 to PCI

S3V66-PCI

3V66 (5:0) leads 33MHz PCI

1.5

3.5

ns

1Guarenteed by design, not 100% tested in production.