ICS952607 datasheet(10/23 Pages) RENESAS

10 / 23 page

Integrated

Circuit

Systems, Inc.

ICS952607

0734A—07/26/05

2C Table: Output Control Register

Control

Function

Bit 7

48MHz_0

2x output drive

0=2x drive

Bit 6

SRCFS

SRC Frequency

Select

-0

Bit 5

Reserved

Bit 4

3V66_1

Output Control

Bit 3

3V66_0

Output Control

Bit 2

PCICLK_F2

Output Control

Bit 1

PCICLK_F1

Output Control

Bit 0

PCICLK_F0

Output Control

2C Table: Reserved Register

Control

Function

Bit 7

3V66_3/VCH

Select

Output Select

Bit 6

Mode Sel1

Bit 5

Mode Sel0

Bit 4

3V66_3/VCH

Output Control

Bit 3

M PLL2 Div3

Bit 2

M PLL2 Div2

Bit 1

M PLL2 Div1

Bit 0

M PLL2 Div0

3V66

VCH

See Table 4: Mode Selection Table

Disable

Enable

Disable

Enable

Disable

Enable

Disable

Enable

Disable

Enable

100MHz

200MHz

Disable

Enable

The decimal representation of M PLL2 Div

(3:0) + 2 is equal to REF divider value for

PLL2

PWD

Byte 5

Pin #

Name

Type

PWD

2x drive

normal

Name

Type

Byte 4

Pin #

PLL Mode Selection Bits

M Divider Programming

bits for Async mode 2&3

Table 3: Linear M/N AGP/PCI Programmable Frequency Example

65.15

32.58

67.44

33.72

65.24

32.62

67.57

33.78

65.34

32.67

67.70

33.85

65.79

32.89

68.01

34.01

66.01

33.01

68.58

34.29

66.14

33.07

68.93

34.47

66.30

33.15

69.34

34.67

66.47

33.24

69.73

34.86

66.68

33.34

69.83

34.91

67.21

33.61

70.01

35.01

Hex B5b3:0

Hex B6b6:0

AGP Freq

PCI Freq

Hex B5b3:0

Hex B6b6:0

AGP Freq

PCI Freq

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