COMMERCIALTEMPERATURERANGE

2

IDTCV126

PROGRAMMABLEFLEXPCCLOCKFORP4PROCESSOR

PIN CONFIGURATION

SSOP/ TSSOP

TOP VIEW

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

FSC/TEST_SEL

REF0

VSS_REF

XTAL_IN

XTAL_OUT

VDD_REF

VSS_CPU

CPU0

CPU0#

VDD_CPU

CPU1

CPU1#

VSSA

VDDA

VTT_PWRGD#/PWRDWN

NC

SDA

SCL

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

VDD_PCI

VSS_PCI

PCI0

PCI1

PCI2

VSS_PCI

VDD_PCI

PCIF1

VDD_48MHz

48MHz

VSS_48MHz

PCIF2

SRC1#

SRC1

VDD_SRC

SRC2

SRC2#

SRC3#

VDD_SRC

SRC4

SRC4#

SRC3

IREF

PCI3

PCIF0

SRC0

SRC0#

VSS_SRC

VDD_SRC

REF1

FSB/TEST_MODE

FSA

VDD_CPU

CPU2

CPU2#

CPU3

CPU3#

VDD_CPU

Pin#

Pin Name

Type

Description

52

XTAL_IN

I

14.318XTALinput

51

XTAL_OUT

O

14.318XTALoutput

54,55

REF[1:0]

O

14.318 MHz

3-6

PCI[3:0]

O

33.33MHz PCI clock

9-11

PCIF[2:0]

O

33.33MHz PCI free running clock

13

USB48

O

48MHz

36,37,39

CPU[3:0]

O

CPU differential clock

40,42,43

CPU#[3:0]

45,46

16-19,

SRC[4:0]

O

SRC differential clock

21-24,

SRC#[4:0]

26,27

49

FSB/TEST_MODE

I

Frequencyselect.Whenintestmode,0

= clock Hi-Z, 1 = clk REF/N

56

FSC/TEST_SEL

I

Frequency select. Select test mode if

pulled to 2V and above when

VTT_PWRGD# assertion.

48

FSA

I

Frequency select, sampled on

VTT_PWRGD# assertion.

33

IREF

I

Referencecurrentfordifferentialoutputs

31

VTT_PWRGD#/PD

I

3.3V LVTTL input, a level-sensitive

strobe used to latch the FS_A, FS_B,

FS_C/TEST_SEL inputs. After

VTT_PWRGD#assertion,becomesareal-

time input for asserting power down

(active HIGH).

30

SDA

I/O

SMBus data

29

SCL

I

SMBus clock

PIN DESCRIPTION

CPU AND SRC SPREAD SPECTRUM

MAGNITUDECONTROL

SMC[2:0]

%

000

- 0.25

001

- 0.5

010

- 0.75

011

- 1

100

±0.125

101

±0.25

110

±0.375

111

±0.5

Symbol

Description

Min

Max

Unit

VDDA

3.3V Core Supply Voltage

4.6

V

VDDIN

3.3V Logic Input Supply Voltage GND - 0.5

4.6

V

TSTG

Storage Temperature

–65

+150

°C

TAMBIENT

Ambient Operating Temperature

0

+70

°C

TCASE

Case Temperature

+115

°C

ESD Prot

Input ESD Protection

2000

V

Human Body Model

ABSOLUTE MAXIMUM RATINGS(1)

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.