Table 2-2.
Local Bus Interface Signals (continued)
Pin
Type
Name
Description
4
Input
-ADS
Processor Address Strobe from the 80386sx. Provides
timing markers for new address and start of cycle.
Tri-stated during a hold acknowledge state.
31
Input
W/-R
Processor Write/Read status. Indicates whether the
CPU cycle is a write or read.
32
Input
D/-C
Processor Data/Control status. Indicates whether the
CPU cycle is a data access or code/control cycle.
34
Input
M/-IO
Memory or I/O select from CPU. Indicates whether
the CPU cycle is a memory access or an I/O.
37
Bidirectional
-READY
Active-low signal indicates the end of a cycle.
-READY is normally controlled by the 82C836 and
should be connected to the 80386sx -READY input.
For external cache and coprocessor support, this
signal can be programmed to operate as an input.
137
Output
-NA (-STCYC)
Next Address Request to the 80386sx. Requests the
CPU to enter pipeline mode if possible. Can be
programmed to operate as a CPU Cycle Start indicator
instead of -NA if desired. Usable as an address latch
(-ADRL) control in either case.
36
Output
HOLD
Hold Request is an active-high output to the processor
that requests bus access for Refresh, DMA or Master
cycles. HOLD should be connected to the processor’s
HOLD input.
35
Input
HLDA
Hold Acknowledge is an active-high input from the
processor indicating when the CPU local bus has been
given up by the processor. HLDA should be
connected to the 80386sx processor’s HLDA pin.
143
Output
NMI
Non-Maskable Interrupt is generated as a result of a
parity error or an I/O channel error (-IOCHCK). NMI
should be connected to the processor’s NMI input.
The 80386sx responds to a low-to-high transition on
NMI.
144
Output
INTR
Interrupt Request is an active-high request to the CPU
to suspend the current process and acknowledge the
request. INTR should be connected to the INTR input
to the CPU.
s Signal Descriptions
Pin Assignments
2-4 Revision 3.0
P R E L I M I N A R Y
Chips and Technologies, Inc.
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