NJU6824 datasheet(21/110 Pages) NJRC

21 / 110 page

NJU6824

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(3) Access to the instruction register

Each instruction resisters is assigned to each address between 0H and FH, and the content of the instruction

Fig4

(4) 8-/16-bit data bus length for display data (in the parallel interface mode)

The 8- or 16-bit data bus length for display data is determined by the “WLS” of the “Data bus length”

instruction.

In the 16-bit data bus mode, instruction data must be 16-bit data (D15 to D0) as well as display data. However,

for the access to the instruction register, the only lower 8-bit data (D7 to D0) of the 16-bit data is valid. For the

access to the DDRAM, all of the 16-bit data (D15 to D0) is valid.

Table8

WLS

Data bus length mode

8-bit

16-bit

(5) Initial display line register

The initial display line resister specifies the line address, corresponding to the initial COM line, by the “Initial

display line” instruction. The initial COM line signifies the common driver, starting scanning the display data in

the DDRAM, and specified by the “Initial COM line” instruction.

The line address, established in the initial display line resister, is preset into the line counter whenever the

FLM signal becomes “1”. At the rising edge of the CL signal, the line counter is counted-up and addressed 384-

bit display data corresponding to the counted-up line address, is latched into the data latch circuit. At the falling

edge of the CL signal, the latched data outputs to the segment drivers.

D0 to D7

WRb

Instruction resister

address set

Instruction resister

contents read

RDb

Instruction resister

address set

Instruction resister

contents read

NJU6824 Datasheet(PDF) 21 Page - New Japan Radio