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89TSF500 Datasheet(PDF) 2 Page - Renesas Technology Corp |
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89TSF500 Datasheet(HTML) 2 Page - Renesas Technology Corp |
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2 / 38 page  2 of 37 April 13, 2005 IDT 89TSF500 Figure 1 89TSF500 Functional Block Diagram Figure 2 Single-Shelf System Request Label Control (RLC) grants Grant Scheduler (GS) request labels back pressure Align Switch (AS) 64 × 64 ZCell Input (ZI) ZCell Output (ZO) CPU Interface (CPIF) backpressure Clock, Reset, and Tick (CRT) Traffic from ingress 89TSF552s Traffic to egress 89TSF552s SerDes Rx SerDes Tx Multicast Mask RAM (MMR) “ZAZ” Line Card(s) Switch Card(s) 89TSF552 CSIX Line Card Functions high-speed serial Backplane 1 89TSF500 |
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