NB2308A

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2

FBK

CLKA1

CLKA2

CLKA3

CLKA4

PLL

MUX

CLKB1

CLKB2

CLKB3

CLKB4

SELECT INPUT

DECODING

Figure 1. Block Diagram

(see Figures 11, 12, 13, 14 and 15 for device specific Block Diagrams)

REF

S2

S1

Extra Divider (−2, −3)

Extra Divider (−5H)

Extra Divider (−3, −4)

B2

B2

B2

Device

Feedback From

Bank A Frequency

Bank B Frequency

NB2308Ax1

Bank A or Bank B

Reference

Reference

NB2308Ax1H

Bank A or Bank B

Reference

Reference

NB2308Ax2

Bank A

Reference

Reference B2

NB2308Ax2

Bank B

2 X Reference

Reference

NB2308Ax3

Bank A

2 X Reference

Reference or Reference (Note 1)

NB2308Ax3

Bank B

4 X Reference

2 X Reference

NB2308Ax4

Bank A or Bank B

2 X Reference

2 X Reference

NB2308Ax5H

Bank A or Bank B

Reference B2

Reference B2

1. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the NB2308Ax2.

Table 2. SELECT INPUT DECODING

S2

S1

Clock A1 − A4

Clock B1 − B4

Output Source

PLL ShutDown

0

0

Three−state

Three−state

PLL

Y

0

1

Driven

Three−state

PLL

N

1

0

Driven (Note 2)

Driven

Reference

Y

1

1

Driven

Driven

PLL

N

2. Outputs inverted on 2308−2 and 2308−3 in bypass mode, S2 = 1 and S1 = 0.