DP83848M datasheet(10/72 Pages) NSC

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1.0 Pin Descriptions

The DP83848M/J pins are classified into the following

interface categories (each interface is described in the

sections that follow):

— Serial Management Interface

— MAC Data Interface

— Clock Interface

— LED Interface

— Reset

— Strap Options

— 10/100 Mb/s PMD Interface

— Special Connect Pins

— Power and Ground pins

Note: Strapping pin option. Please see Section 1.6 for

strap definitions.

All DP83848M/J signal pins are I/O cells regardless of the

particular use. The definitions below define the functional-

ity of the I/O cells for each pin.

1.1 SERIAL MANAGEMENT INTERFACE

1.2 MAC DATA INTERFACE

Type: I

Input

Type: O

Output

Type: I/O

Input/Output

Type: PD,PU Internal Pulldown/Pullup

Type: S

Strapping Pin (All strap pins have weak in-

ternal pull-ups or pull-downs. If the default

strap value is needed to be changed then an

external 2.2 k

Ω resistor should be used.

Please see Section 1.6 for details.)

Signal Name

Type

Pin #

Description

MDC

MANAGEMENT DATA CLOCK: Synchronous clock to the MDIO

management data input/output serial interface which may be

asynchronous to transmit and receive clocks. The maximum clock

rate is 25 MHz with no minimum clock rate.

MDIO

I/O

MANAGEMENT DATA I/O: Bi-directional management instruc-

tion/data signal that may be sourced by the station management

entity or the PHY. This pin requires a 1.5 k

Ω pullup resistor.

Signal Name

Type

Pin #

Description

TX_CLK

MII TRANSMIT CLOCK: 25 MHz Transmit clock output in 100

Mb/s mode or 2.5 MHz in 10 Mb/s mode derived from the 25 MHz

reference clock.

TX_EN

I, PD

MII TRANSMIT ENABLE: Active high input indicates the pres-

ence of valid data inputs on TXD[3:0].

TXD_0

TXD_1

TXD_2

TXD_3

I, PD

MII TRANSMIT DATA: Transmit data MII input pins, TXD[3:0],

that accept data synchronous to the TX_CLK (2.5 MHz in 10 Mb/s

mode or 25 MHz in 100 Mb/s mode).

RX_CLK

MII RECEIVE CLOCK: Provides the 25 MHz recovered receive

clocks for 100 Mb/s mode and 2.5 MHz for 10 Mb/s mode.

RX_DV

O, PD

MII RECEIVE DATA VALID: Asserted high to indicate that valid

data is present on the corresponding RXD[3:0].

RX_ER

S, O, PU

MII RECEIVE ERROR: Asserted high synchronously to RX_CLK

to indicate that an invalid symbol has been detected within a re-

ceived packet in 100 Mb/s mode.

RXD_0

RXD_1

RXD_2

RXD_3

S, O, PD

MII RECEIVE DATA: Nibble wide receive data signals driven syn-

chronously to the RX_CLK, 25 MHz for 100 Mb/s mode, 2.5 MHz

for 10 Mb/s mode). RXD[3:0] signals contain valid data when

RX_DV is asserted.

CRS/LED_CFG

S, O, PU

MII CARRIER SENSE: Asserted high to indicate the receive me-

dium is non-idle.

DP83848M Datasheet(PDF) 10 Page - National Semiconductor (TI)

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