Nexperia

74LVC1T45; 74LVCH1T45

Dual supply translating transceiver; 3-state

6. Pinning information

6.1. Pinning

74LVC1T45

74LVCH1T45

VCC(A)

VCC(B)

GND

A

B

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1

2

3

6

DIR

5

4

Fig. 3. Pin configuration SOT363-2

(TSSOP6)

74LVC1T45

74LVCH1T45

GND

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VCC(A)

A

DIR

VCC(B)

B

Transparent top view

2

3

1

5

4

6

Fig. 4. Pin configuration SOT886

(XSON6)

74LVC1T45

74LVCH1T45

GND

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VCC(A)

A

DIR

VCC(B)

B

Transparent top view

2

3

1

5

4

6

Fig. 5. Pin configuration SOT1115

and SOT1202 (XSON6)

6.2. Pin description

Table 3. Pin description

Symbol

Pin

Description

VCC(A)

1

supply voltage port A and DIR

GND

2

ground (0 V)

A

3

data input or output

B

4

data input or output

DIR

5

direction control

VCC(B)

6

supply voltage port B

7. Functional description

Table 4. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.

Supply voltage

Input

Input/output [1]

VCC(A), VCC(B)

DIR

A

B

1.2 V to 5.5 V

L

A = B

input

1.2 V to 5.5 V

H

input

B = A

GND [2]

X

Z

Z

[1] The input circuit of the data I/O is always active.

[2] When either VCC(A) or VCC(B) is at GND level, the device goes into suspend mode.

74LVC_LVCH1T45

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© Nexperia B.V. 2022. All rights reserved

Product data sheet

Rev. 9 — 10 February 2022

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