AD5934 datasheet(13/32 Pages) AD

13 / 32 page

AD5934

Rev. 0 | Page 13 of 32

FREQUENCY SWEEP COMMAND SEQUENCE

The following sequence must be followed to implement a

frequency sweep.

Enter standby mode.

Prior to issuing a Start Frequency Sweep command, the device

must be placed in a standby mode by issuing an Enter Standby

Mode command to the CONTROL register (Register 80 h). In

this mode, the VOUT and VIN pins are connected internally to

ground so there is no dc bias across the external impedance or

between the impedance and ground.

Enter initialize mode.

In general, high Q complex circuits require a long time to

reach steady state. To facilitate the measurement of such

impedances, this mode allows the user full control of the

settling time requirement before entering start frequency

sweep mode where the impedance measurement takes place.

An Initialize with Start Frequency Command to the

CONTROL register enters initialize mode. In this mode the

impedance is excited with the programmed start frequency

but no measurement takes place. The user times out the

required settling time before issuing a Start Frequency

Sweep command to the CONTROL register to enter the

start frequency sweep mode.

Enter start frequency sweep mode.

The user enters this mode by issuing a Start Frequency Sweep

command to the control register. In this mode, the ADC

starts measuring after the programmed Number of Settling

Time Cycles has elapsed. The user can program an integer

number of output frequency cycles (settling time cycles) to

measurement at each frequency point (see Figure 28).

The DDS output signal is passed through a programmable gain

stage in order to generate the four ranges of peak-to-peak output

excitation signals listed in Table 6. The peak-to-peak output

excitation voltage is selected by setting Bit D10 and Bit D9 in

the CONTROL register—see the Control Register section—

and is made available at the VOUT pin.

PHASE

ACCUMULATOR

(27 BITS)

VOUT

DAC

R(GAIN)

VBIAS

Figure 16. AD5934 Transmit Stage

RECEIVE STAGE

The receive stage comprises a current–to-voltage amplifier,

followed by a programmable gain amplifier (PGA), antialiasing

filter, and ADC. The receive stage schematic is shown in

Figure 17. The unknown impedance is connected between the

VOUT and VIN pins. The first stage current-to-voltage amplifier

configuration means that a voltage present at the VIN pin is a

virtual ground with a dc value set at VDD/2. The signal current

that is developed across the unknown impedance flows into the

VIN pin and develops a voltage signal at the output of the current-

to-voltage converter. The gain of the current-to voltage amplifier

is determined by a user-selectable feedback resistor connected

between Pins 4 (RFB) and Pin 5 (VIN). It is important for the user

to choose a feedback resistance value which, in conjunction with

the selected gain of the PGA stage, maintains the signal within the

linear range of the ADC (0 V to VDD).

The PGA allows the user to gain the output of the current-to-

voltage amplifier by a factor of 5 or 1 depending upon the status

of Bit D8 in the CONTROL register (see the Register Map section

to the input of the 12-bit, 250 kSPS ADC.

× R

VIN

VDD/2

RFB

ADC

LPF

Figure 17. AD5934 Receive Stage

The digital data from the ADC is passed directly to the DSP core

of the AD5934 which performs a DFT on the sampled data.

DFT OPERATION

A DFT is calculated for each frequency point in the sweep. The

AD5934 DFT algorithm is represented by

()

))

sin(

)

)(cos(

(

)

(

1023

−

∑

where X(f) is the power in the signal at the frequency point f, x(n)

is the ADC output, with the cos(n) and sin(n) the sampled test

vectors provided by the DDS core at the frequency f.

The multiplication is accumulated over 1024 samples for each

frequency point. The result is stored in two, 16-bit registers

representing the real and imaginary components of the result. The

data is stored in twos complement format.

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