LTM8063 datasheet(11/26 Pages) AD

11 / 26 page

LTM4709

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

The LTM4709 is a low voltage, ultralow noise, and ultra-

fast transient response μModule linear regulator. The

device supplies up to triple 3A with a typical dropout volt-

age of 45mV. The high bandwidth and high PSRR allow

for the use of a single small ceramic capacitor for input

and output, saving bulk capacitance, space, and cost. The

LTM4709 is ideal for high-performance FPGAs, micropro-

cessors, RF communication and noise-sensitive supply

applications.

Output Voltage

Output voltages are digitally selectable in 50mV incre-

ments from 0.5V to 1.2V; 100mV increments from 1.2V

to 1.8V; and discrete levels at 2V, 2.5V, 3V, 3.3V and 4.2V.

The tri-level input pins, VO10, VO11, VO12, VO20, VO21, VO22,

VO30, VO31, VO32 set the output voltage. Table 1 illustrates

the three-bit digital word to output voltage relationship

based on setting these pins high, low, or floating. An

input logic low state is guaranteed with less than 300mV

referenced to GND and a logic high state is guaranteed

with greater than 1.9V. The range from 950mV to 1.15V

defines the logic Hi-Z (input floating) state. These pins

may be tied high by either pin strapping them to BIASn

or driving them with digital ports. Pins that float may

either float or require logic that has Hi-Z output capability.

This allows the output voltage to be dynamically changed

if necessary.

Voltage Reference

The voltage reference VREF1,2,3 pin is the voltage output

of the internal current reference feeding into a resistor.

A 2.2μF ceramic capacitor has been integrated between

the VREF and GND inside the LTM4709 to decrease the

reference voltage noise and soft-start the output when the

device is enabled. The VREF pin must not be DC loaded

by anything except for applications that need to be paral-

leled with other channels. See the Paralleling Devices for

Higher Output Current section for more details.

Table 1. VOUT Selection Matrix

VOUT

(V)

VOX0

VOX1

VOX2

0.500

0.550

0.600

0.650

0.700

0.750

0.800

0.850

0.900

0.950

1.000

1.050

1.100

1.150

1.200

1.300

1.400

1.500

1.600

1.700

1.800

2.000

2.500

3.000

3.300

4.200

Note: X is 1, 2, or 3 representing channel; 0 = Low, Z = Hi-Z (Float),

1 = High.

Enable

The EN1,2,3 pin enables/disables the output and reference

pin. Pulling EN pin low places the regulator into shut-

down mode. In shutdown mode, the quiescent current

decreases to less than 10μA.

Drive the EN pin with either a digital logic port, an

open-collector NPN or an open-drain NMOS terminated

with a pull-up resistor to BIAS1,2,3. The pull-up resistor

must be less than 200k to meet the VOH condition of the

EN pin. If not used, connect the EN pin to BIAS.

LTM8063 Datasheet(PDF) 11 Page - Analog Devices

LTM8063 Datasheet(HTML) 11 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Datasheet Download

Link URL