AD8188ARUZ-R7 datasheet(16/24 Pages) AD

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AD8188/AD8189

Rev. 0 | Page 16 of 24

VREF

10kΩ

1µF

CAP MUST BE LARGE

ENOUGH TO ABSORB

TRANSIENT CURRENTS

WITH MINIMUM BOUNCE.

Figure 49. Alternate Method for Synthesis of a False Ground Reference

AC-COUPLED INPUTS

Using ac-coupled inputs presents an interesting challenge for

video systems operating from a single 5 V supply. In NTSC and

PAL video systems, 700 mV is the approximate difference

between the maximum signal voltage and black level. It is

assumed that sync has been stripped. However, given the two

pathological cases shown in Figure 50, a dynamic range of twice

the maximum signal swing is required if the inputs are to be

ac-coupled. A possible solution is to use a dc restore circuit

before the mux.

+700mV

–700mV

+5V

GND

VAVG

VSIGNAL

VREF

WHITE LINE WITH BLACK PIXEL

BLACK LINE WITH WHITE PIXEL

VINPUT = VREF + VSIGNAL

VREF ~ VAVG

VREF IS A DC VOLTAGE

SET BY THE RESISTORS

Figure 50. Pathological Case for Input Dynamic Range

TOLERANCE TO CAPACITIVE LOAD

Op amps are sensitive to reactive loads. A capacitive load at the

output appears in parallel with an effective resistance (REFF) of

REFF

= (RL || rO)

where RL is the discrete resistive load, and rO is the open loop

output impedance, approximately 15 Ω for these muxes.

The load pole (fLOAD) at

EFF

LOAD

can seriously degrade phase margin and, therefore, stability. The

old workaround is to place a small series resistor directly at the

output to isolate the load pole. While effective, this ruse also

affects the dc and termination characteristics of a 75 Ω system.

The AD8188 and AD8189 are built with a variable compensation

scheme that senses the output reactance and trades bandwidth

for phase margin, ensuring faster settling and lower overshoot

at higher capacitive loads.

SECONDARY SUPPLIES AND SUPPLY BYPASSING

The high current output transistors are given their own supply

pins (Pin 15, Pin 17, Pin 19, and Pin 21) to reduce supply noise

on-chip and to improve output isolation. Because these

secondary, high current supply pins are not connected on-chip

to the primary analog supplies, VCC/VEE (Pin 6, Pin 7, Pin 9,

Pin 11, Pin 13, and Pin 24), some care should be taken to ensure

that the supply bypass capacitors are connected to the correct

pins. At a minimum, the primary supplies should be bypassed.

Pin 6 and Pin 7 can be a convenient place to accomplish this.

Stacked power and ground planes are a convenient way to

bypass the high current supply pins (see Figure 51).

MUX1

MUX2

MUX3

0.1µF

1µF

VCC

DVCC

VEE

OUT2

VCC

OUT1

VEE

OUT0

VCC

IN0A

IN0B

VEE

IN1B

VEE

IN2B

VEE

VCC

IN2A

VREF

IN1A

DGND

SEL A/B

Figure 51. Detail of Primary and Secondary Supplies

SPLIT-SUPPLY OPERATION

Operating from split supplies (for example, [+3 V/−2 V] or

±2.5 V) simplifies the selection of the VREF voltage and load

resistor termination voltage. In this case, it is convenient to tie

VREF to ground. The logic inputs are internally level-shifted to

allow the digital supplies and logic inputs to operate from 0 V

and 5 V when powering the analog circuits from split supplies.

The maximum voltage difference between DVCC and VEE must

not exceed 8 V (see Figure 52).

8V MAX

(+5V)

(0V)

(+2.5V)

(–2.5V)

DVCC

DGND

VCC

VEE

DIGITAL SUPPLIES

ANALOG SUPPLIES

Figure 52. Split-Supply Operation

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