Nexperia

74HC4094; 74HCT4094

8-stage shift-and-store bus register

7. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = HIGH-impedance OFF-state; NC = no change;

↑ = positive-going transition; ↓ = negative-going transition;

Q6S = the data in register stage 6 before the LOW to HIGH clock transition;

Q7S = the data in register stage 7 before the HIGH to LOW clock transition.

Inputs

Parallel outputs

Serial outputs

CP

OE

STR

D

QP0

QPn

QS1

QS2

↑

L

X

X

Z

Z

Q6S

NC

↓

L

X

X

Z

Z

NC

Q7S

↑

H

L

X

NC

NC

Q6S

NC

↑

H

H

L

L

QPn -1

Q6S

NC

↑

H

H

H

H

QPn -1

Q6S

NC

↓

H

H

H

NC

NC

NC

Q7S

001aaf117

CLOCK INPUT

DATA INPUT

STROBE INPUT

OUTPUT ENABLE INPUT

INTERNAL Q0S (FF 0)

OUTPUT QP0

INTERNAL Q6S (FF 6)

OUTPUT QP6

SERIAL OUTPUT QS1

SERIAL OUTPUT QS2

Z-state

Z-state

At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the

QSn outputs.

Fig. 7. Timing diagram

74HC_HCT4094

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Product data sheet

Rev. 9 — 22 October 2021

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