LM5010ASDX datasheet(15/17 Pages) NSC

15 / 17 page

Applications Information (Continued)

In Figure 10, Cff is added across R1 to AC-couple the ripple

at V

OUT directly to the FB pin. This allows the ripple at VOUT

to be reduced, in some cases considerably, by reducing R3.

In the circuit of Figure 6, the ripple at V

OUT ranged from 50

mVp-p at V

IN = 6V to 320 mVp-p at VIN = 60V. By adding a

1000 pF capacitor at Cff and reducing R3 to 0.75

Ω, the V

OUT

ripple was reduced by 50%, ranging from 25 mVp-p to 160

mVp-p.

To reduce V

OUT ripple further, the circuit of Figure 11 can be

used. R3 has been removed, and the output ripple amplitude

is determined by C2’s ESR and the inductor ripple current.

RA and CA are chosen to generate a 40-50 mVp-p sawtooth

at their junction, and that voltage is AC-coupled to the FB pin

via CB. In selecting RA and CA, V

OUT is considered a virtual

ground as the SW pin switches between V

IN and -1V. Since

the on-time at SW varies inversely with V

IN, the waveform

amplitude at the RA/CA junction is relatively constant. R1

and R2 must typically be increased to more than 10k each to

not significantly attenuate the signal provided to FB through

CB. Typical values for the additional components are RA =

200k, CA = 680 pF, and CB = 0.01 µF.

INCREASING THE CURRENT LIMIT THRESHOLD

The current limit threshold is nominally 1.25A, with a mini-

mum guaranteed value of 1.0A. If, at maximum load current,

the lower peak of the inductor current (I

PK- in Figure 5)

exceeds 1.0A, resistor R

CL must be added between SGND

and I

SEN to increase the current limit threshold to equal or

exceed that lower peak current. This resistor diverts some of

the recirculating current from the internal sense resistor so

that a higher current level is needed to switch the internal

current limit comparator. I

PK- is calculated from:

(14)

where I

O(max) is the maximum load current, and IOR(min) is

the minimum ripple current calculated using Equation 13.

CL is calculated from:

(15)

where 0.11

Ω is the minimum value of the internal resistance

from SGND to ISEN. The next smaller standard value resis-

tor should be used for R

CL. With the addition of RCL, and

when the circuit is in current limit, the upper peak current out

of the SW pin (I

PK in Figure 4) can be as high as:

where I

OR(max) is calculated using Equation 12. The inductor

L1 and diode D1 must be rated for this current. If I

PK exceeds

2A , the inductor value must be increased to reduce the

ripple amplitude. This will necessitate recalculation of

OR(min),IPK-, and RCL.

Increasing the circuit’s current limit will increase power dis-

sipation and the junction temperature within the LM5010A.

See the next section for guidelines on this issue.

PC BOARD LAYOUT and THERMAL CONSIDERATIONS

The LM5010A regulation, over-voltage, and current limit

comparators are very fast, and will respond to short duration

noise pulses. Layout considerations are therefore critical for

optimum performance. The layout must be as neat and

compact as possible, and all the components must be as

close as possible to their associated pins. The two major

current loops have currents which switch very fast, and so

the loops should be as small as possible to minimize con-

ducted and radiated EMI. The first loop is that formed by C1,

through the VIN to SW pins, L1, C2, and back to C1. The

second loop is that formed by D1, L1, C2, and the SGND and

ISEN pins. The ground connection from C2 to C1 should be

as short and direct as possible, preferably without going

through vias. Directly connect the SGND and RTN pin to

each other, and they should be connected as directly as

possible to the C1/C2 ground line without going through vias.

The power dissipation within the IC can be approximated by

determining the total conversion loss (P

IN -POUT), and then

subtracting the power losses in the free-wheeling diode and

the inductor. The power loss in the diode is approximately:

D1 =IO xVF x (1-D)

where Io is the load current, V

F is the diode’s forward voltage

drop, and D is the duty cycle. The power loss in the inductor

is approximately:

L1 =IO

2 xR

L x 1.1

where R

L is the inductor’s DC resistance, and the 1.1 factor

is an approximation for the AC losses. If it is expected that

the internal dissipation of the LM5010A will produce high

junction temperatures during normal operation, good use of

the PC board’s ground plane can help considerably to dissi-

pate heat. The exposed pad on the IC package bottom

should be soldered to a ground plane, and that plane should

both extend from beneath the IC, and be connected to

exposed ground plane on the board’s other side using as

many vias as possible. The exposed pad is internally con-

nected to the IC substrate. The use of wide PC board traces

at the pins, where possible, can help conduct heat away

from the IC. The four No Connect pins on the TSSOP

package are not electrically connected to any part of the IC,

and may be connected to ground plane to help dissipate

heat from the package. Judicious positioning of the PC

board within the end product, along with the use of any

available air flow (forced or natural convection) can help

reduce the junction temperature.

20153849

FIGURE 11. Low Output Ripple Using Ripple Injection

LM5010ASDX Datasheet(PDF) 15 Page - National Semiconductor (TI)

LM5010ASDX Datasheet(HTML) 15 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Datasheet Download

Link URL