CDB4265

DS657DB1

3

LIST OF FIGURES

Figure 1. CDB4265 Controls Tab.................................................................................................... 7

Figure 2. S/PDIF Rx Controls Tab .................................................................................................. 8

Figure 3. Register Maps Tab........................................................................................................... 9

Figure 4. Block Diagram................................................................................................................ 18

Figure 5. CS4265 .......................................................................................................................... 19

Figure 6. Analog Inputs ................................................................................................................. 20

Figure 7. Analog Outputs .............................................................................................................. 21

Figure 8. S/PDIF I/O...................................................................................................................... 22

Figure 9. Control Port.................................................................................................................... 23

Figure 10. FPGA ........................................................................................................................... 24

Figure 11. Discrete Clock Routing and Level Shifting................................................................... 25

Figure 12. Power........................................................................................................................... 26

Figure 13. Silk Screen................................................................................................................... 27

Figure 14. Topside Layer .............................................................................................................. 28

Figure 15. Bottom side Layer ........................................................................................................ 29

LIST OF TABLES

Table 1. MCLK Source.................................................................................................................. 12

Table 2. CS4265 Subclock Source ............................................................................................... 13

Table 3. SDIN2 Source ................................................................................................................. 14

Table 4. SDIN1 Source ................................................................................................................. 14

Table 5. TXSDIN Source............................................................................................................... 15

Table 6. System Connections ....................................................................................................... 16

Table 7. System Jumper Settings .................................................................................................17

Table 8. Revision History .............................................................................................................. 30