ON*

Normal Operation

OFF

Power down active

ON

Selects configuration register for

operating mode

OFF*

Select hardware pins for operating

mode

ON*

Selects MDATA from modulator

OFF

Selects TDATA as filter input

ON*

Sets TDATA input to logic 0

OFF

Enables TDATA from J1 header

ABC

Output Word Rate

0 0 0

62.5

1 0 0

125

0 1 0

250

1 1 0

500

0 0 1

1000

1 0 1

2000

0 1 1

4000

Selection

via hardware

pins

DECA

DECB

DECC

PWDN

H/S

CSEL

TDATA

OFF = OPEN = 1

*Default to use Figure 6 interface.

Table 2. S4 DIP switch selections

ON*

Do not use offset register

OFF

Use offset register

ON*

Disable offset register calibration

OFF

Enable offset register calibration

ON

Sets SID to Logic 0

OFF* Allows pull-up on SID line

ON

Sets ERR to logic 0

OFF* Allows CS5322 ERROR output

ON

Select status register

OFF* Select conversion data register

ON*

Chip select active

OFF

Chip select inactive

ON

Enables write mode via SID pin

OFF* Enables read mode via SOD pin

USEOR

ORCAL

SID

ERR

RSEL

CS

R/W

OFF = OPEN = 1

*Default to use Figure 6 interface.

Table 1. S3 DIP Switch Selections

13

12

10

9

8

11

U3F

U3E

U3D

5

6

U3C

SCLK

SOD

DRDY

+5V

+5V

JP6

0.1

10

10

µF

+

DRDY

SCLK

SOD

+5V

8

9

R4

56

U3, U4 = 74HC04

C35

C5

DRDY

SOD

SCLK

14

U4D

U4F

7

U4C

3

4

U4B

1

2

U4A

10

11

U4E

12

13

U4

From

Figure

4

Figure 5. Serial Latch Interface on CDB5321 (Rev B) board

CDB5321

20

DS88DB2