M37544G2SP datasheet(17/68 Pages) RENESAS

17 / 68 page

7544 Group

Rev.1.04

2004.06.08

page 17 of 66

REJ03B0012-0104Z

Fig. 17 Block diagram of ports (1)

(6)Port P12

Serial I/O clock output

Serial I/O mode selection bit

Serial I/O enable bit

Serial I/O synchronous

clock selection bit

Direction

Data bus

Port latch

Serial I/O clock input

P10, P12

input level

selection bit

(2)Ports P01,P02,P04–P07

Direction

Data bus

Port latch

Pull-up control

To key input interrupt

generating circuit

(1)Port P00

Direction

Data bus

Port latch

Pull-up control

To key input interrupt

generating circuit

CNTR1 interrupt input

(3)Port P03

Direction

Data bus

Port latch

Pull-up control

To key input interrupt

generating circuit

Timer output

P03/TXOUT

output valid

(5)Port P11

Data bus

Port latch

Serial I/O output

P11/TxD P-channel output disable bit

Direction

Serial I/O enable bit

Transmit enable bit

(4)Port P10

Direction

Data bus

Port latch

Serial I/O enable bit

Receive enable bit

Serial I/O input

P10, P12

input level

selection bit

*P10, P12, P34, and P37 input level are switched to the CMOS/TTL level by the port P1P3 control register.

When the TTL level is selected, there is no hysteresis characteristics.

P00 key-on wakeup

selection bit

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