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L8C201 Datasheet(PDF) 5 Page - LOGIC Devices Incorporated

Part # L8C201
Description  512/1K/2K/4K x 9-bit Asynchronous FIFO
PDF  22 Pages
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Manufacturer  LODEV [LOGIC Devices Incorporated]
Direct Link  http://www.logicdevices.com
Logo LODEV - LOGIC Devices Incorporated

L8C201 Datasheet(HTML) 5 Page - LOGIC Devices Incorporated

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DEVICES INCORPORATED
5
L8C201/202/203/204
512/1K/2K/4K x 9-bit Asynchronous FIFO
03/04/99–LDS.8C201/2/3/4-H
FIFO Products
L8C201/202/203/204–
25
15
12
10
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
tRLRL
Read Cycle Time (MHz)
35
25
20
15
tRLQV
Read Low to Output Valid (Access Time)
25
15
12
10
tRHRL
Read High to Read Low (Notes 8, 9)
10
10
8
5
tRLRH
Read Low to End of Read Cycle (Notes 8, 9)
25
15
12
10
tRHQV
Read High to Output Valid
5
5
5
5
tRHQZ
Read High to Output High Z (Note 14)
20
15
15
15
tWLWL
Write Cycle Time (Note 9)
35
25
20
15
tWLWH
Write Low to Write High (Notes 8, 9)
25
15
12
10
tWHWL
Write High to End of Write Cycle (Notes 8, 9)
10
10
8
5
tDVWH
Data Valid to Write High (Notes 8, 9)
15
10
8
8
tWHDX
Write High to Data Change (Notes 8, 9)
00
00
tSLSH
Reset Cycle Time (Notes 9, 10)
25
15
12
10
tSLWL
Reset Low to Write Low (Notes 9, 10)
35
25
20
15
tWHSH
Write High to Reset High (Notes 9, 10)
25
15
12
10
tRHSH
Read High to Reset High (Notes 9, 10)
25
15
12
10
tSHWL
Reset High to Write Low (Notes 9, 10)
10
10
8
5
tSLEL
Reset Low to Empty Flag Low
25
15
12
10
tSLHH
Reset Low to Half-Full Flag High
25
15
12
10
tSLFH
Reset Low to Full Flag High
25
15
12
10
SWITCHING CHARACTERISTICS Over Commercial and Industrial Operating Range
ASYNCHRONOUS AND RESET TIMING (ns)
ASYNCHRONOUS READ AND WRITE OPERATION
tRLQV
R
tRLRL
tRLQV
tRLRH
tRHRL
tRHQV
tRHQZ
tDVWH
tWHDX
tWLWH
tWLWL
tWHWL
DATA-IN VALID
DATA-IN VALID
DATA-OUT VALID
DATA-OUT VALID
W
Q8-0
D8-0
RESET TIMING
tSLSH
W
tSLEL
tSLHH, tSLFH
tSLWL
tWHSH
tRHSH
tSHWL
RS
R
EF
HF, FF



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