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PCI7410

SLLA247 – JULY 2006

The PCI7410 design provides PCI bus master bursting, and it is capable of transferring a cacheline of data at

132M bytes/s after connection to the memory controller. Because PCI latency can be large, deep FIFOs are

provided to buffer the 1394 data.

The PCI7410 controller provides physical write posting buffers and a highly-tuned physical data path for SBP-2

performance. The PCI7410 controller also provides multiple isochronous contexts, multiple cacheline burst

transfers, advanced internal arbitration, and bus-holding buffers.

The PCI7410 PHY-layer provides the digital and analog transceiver functions needed to implement a two-port

node in a cable-based 1394 network. Each cable port incorporates two differential line transceivers. The

transceivers include circuitry to monitor the line conditions as needed for determining connection status, for

initialization and arbitration, and for packet reception and transmission.

The PCI7410 PHY-layer requires only an external 24.576-MHz crystal as a reference for the cable ports. An

external clock may be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop

(PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to

provide the clock signals that control transmission of the outbound encoded strobe and data information. A

49.152-MHz clock signal is supplied to the integrated LLC for synchronization and is used for resynchronization

of the received data. Data bits to be transmitted through the cable ports are received from the integrated LLC

and are latched internally in synchronization with the 49.152-MHz system clock. These bits are combined

serially, encoded, and transmitted at 98.304M, 196.608M, or 393.216M bits/s (referred to as S100, S200, or

S400 speeds, respectively) as the outbound data-strobe information stream. During transmission, the encoded

data information is transmitted differentially on the twisted-pair B (TPB) cable pair(s), and the encoded strobe

information is transmitted differentially on the twisted-pair A (TPA) cable pair(s).

Various implementation specific functions and general-purpose inputs and outputs are provided through several

multifunction terminals. These terminals present a system with options, such as PCI LOCK and parallel IRQs.

ACPI-complaint general-purpose events may be programmed and controlled through the multifunction terminals,

and an ACPI-compliant programming interface is included for the general-purpose inputs and outputs.

The PCI7410 controller is compliant with the latest PCI Bus Power Management Specification, and provides

several low-power modes, which enable the host power system to further reduce power consumption. The

PCI7410 controller also has a four-pin interface compatible with both the TI TPS2211 and TPS2221 power

switches.

An advanced CMOS process achieves low power consumption and allows the PCI7410 controller to operate at

PCI clock rates up to 33 MHz.

NOTE:

This product is for high-volume PC applications only. For a complete datasheet or

more information contact support@ti.com.

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