SC1404ITSTR datasheet(20/27 Pages) SEMTECH

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SC1404

PRELIMINARY

POWER MANAGEMENT

As with any high frequency switching regulator design, a good PCB

layout is very essential in order to achieve optimum noise, effi-

ciency, and stability performance of the converter. Before starting

to layout the PCB, a careful layout strategy is strongly recom-

mended. See the PCB layout in the SC1404 Evaluation Kit manual

for example. In most applications, we recommend to use FR4

with 4 or more layers and at least 2 oz copper (for output current

up to 6A). Use at least one inner layer for ground connection. And

it is always a good practice to tie signal ground and power ground

at one single point so that the signal ground is not easily contami-

nated. Also be sure that high current paths have low inductance

and resistance by making trace widths as wide as possible and

lengths as short as possible. Properly decouple lines that pull

large amounts of current in short periods of time. The following

step by step layout strategy should be used in order to fully utilize

the potential of SC1404.

Step #1. Power train components placement.

a. Power train arrangement.

Place power train components first. The figure below shows the

recommended power train arrangement. Q1 is the main switching

FET, Q2 is the synchronous Rectifier FET, D1 is the Schottky diode

and L1 is the output inductor. The phase node, where the source

Layout Guidelines

of the upper switching FET and the drain of the synchronous recti-

fier meets, since it switches at very high rate of speed, is generally

the largest source of common-mode noise in the converter circuit.

It should be kept to a minimum size consistent with its connectiv-

ity and current carrying requirements. Also place the Schottky di-

ode as close to the phase node as possible to minimize the trace

inductance, to reduce the efficiency loss due to the current ramp-

up and down time. This becomes extremely important when the

converter needs to handle high di/dt requirements.

b. Current Sense.

Minimize the length of current sense signal trace. Keep it less

than 15mm. Kelvin connections should be used; try to keep the

traces parallel to each other and route them close to each other

as much as possible. Even though SC1404 implements Virtual

Current Sense scheme, the current sense signal is sampled by

the SC1404 to determine the PSAVE threshold. See the following

figure for a Kelvin connection of the current sense signal.

c. Gate Drive.

SC1404 has built-in gate drivers capable of sinking/sourcing 1A

peaks. Upper gate drive signals are noisier than the lower ones.

Therefore, place them away from sensitive analog circuitries. Make

sure the lower gate traces are as close as possible to the IC pins

and both upper and lower gate traces as wide as possible.

Step #2: PWM controller placement (pins) and signal ground is-

land.

Connect all analog grounds to a separate solid copper island

plane, which connects to the SC1404’s GND pin. This includes

REF, COMP3, COMP5, SYNC, RUN/ON3, ON5, PSV# and RESET#.

Step #3: Ground plane arrangement.

There are several ways to tie the different grounds together. Since

this is a buck topology converter, the output ground is relatively

quieter than the input ground. Therefore connect analog ground

to power ground at the output side. Often it is useful to use a

separate ground symbol for the two grounds, and tie the two

grounds together at a single point through a 0

Ω resistor. The

power ground for the input side and the power ground for the

output side is the same ground and they can be tied together

using internal planes.

CSH

CSL

SC1404

Rcs

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