GWIXP425BBT datasheet(47/134 Pages) INTEL

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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor

Datasheet

March 2005

Document Number: 252479, Revision: 005

GPIO[13]

I/O

General purpose input/output pins. May be configured as an input

or an output. Default after reset is to be configured as inputs.

Should be pulled low using a 10-K

Ω resistor when not being utilized

in the system.

GPIO[14]

I/O

Can be configured similar to GPIO Pin 13 or as a clock output.

Configuration as an output clock can be set at various speeds of up

to 33.33 MHz with various duty cycles. Configured as an input,

upon reset.

Should be pulled low though a 10-K

Ω resistor when not being

utilized in the system.

GPIO[15]

CLKOU

T/VO

I/O

Can be configured similar to GPIO Pin 13 or as a clock output.

Configuration as an output clock can be set at various speeds of up

to 33.33 MHz with various duty cycles. Configured as an output,

upon reset. Can be used to clock the expansion interface, after

reset.

Should be pulled low though a 10-K

Ω resistor when not being

utilized in the system.

Table 17.

JTAG Interface

Name

Power

Reset1

Reset2

Type†

Description

JTG_TMS

VI/PE

Test mode select for the IEEE 1149.1 JTAG interface.

JTG_TDI

VI/PE

Input data for the IEEE 1149.1 JTAG interface.

JTG_TDO

Output data for the IEEE 1149.1 JTAG interface.

JTG_TRST_N

VI/PE

Used to reset the IEEE 1149.1 JTAG interface.

The JTG_TRST_N signal must be asserted (driven low) during

power-up, otherwise the TAP controller may not be initialized

properly, and the processor may be locked.

When the JTAG interface is not being used, the signal must be

pulled low using a 10-K

Ω resistor.

JTG_TCK

Used as the clock for the IEEE 1149.1 JTAG interface.

While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.

After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of

PLL_LOCK, all signals reflect the value shown in the RESET column.

†

For a legend of the Type codes, see Table 5 on page 33.

Table 16.

GPIO Interface (Sheet 2 of 2)

Name

Power

Reset1

Reset2

Type†

Description

While PWRON_RESET_N is deasserted use Power On Reset column for the pin state.

After deassertion of PWRON_RESET_N, and deassertion of RESET_IN_N, and assertion of

PLL_LOCK, all signals reflect the value shown in the RESET column.

†

For a legend of the Type codes, see Table 5 on page 33.

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