Nexperia

74HC112; 74HCT112

Dual JK flip-flop with set and reset; negative-edge trigger

4. Functional diagram

RD

FF

SD

10

Q

1Q

2Q

1Q

2Q

5

9

3

11

1

13

6

aaa-024306

7

Q

1SD

CP

2CP

1CP

2J

1J J

2

12

2K

1K

K

2SD

14

1RD 2RD

15

4

Fig. 1. Logic symbol

4

3

1

5

6

2

15

S

1J

C1

1K

R

aaa-024307

10

11

13

9

7

12

14

S

1J

C1

1K

R

Fig. 2. IEC logic symbol

aaa-024308

C

K

J

S

R

CP

C

C

C

C

C

C

C

C

Q

Q

C

Fig. 3. Logic diagram (one flip-flop)

5. Pinning information

5.1. Pinning

74HC112

74HCT112

1CP

VCC

1K

1RD

1J

2RD

1SD

2CP

1Q

2K

1Q

2J

2Q

2SD

GND

2Q

aaa-024309

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 4. Pin configuration SOT109-1 (SO16)

74HC112

74HCT112

1CP

VCC

1K

1RD

1J

2RD

1SD

2CP

1Q

2K

1Q

2J

2Q

2SD

GND

2Q

aaa-024310

1

2

3

4

5

6

7

8

10

9

12

11

14

13

16

15

Fig. 5. Pin configuration SOT403-1 (TSSOP16)

74HC_HCT112

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© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 4 — 11 January 2021

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