MD8412B
Ver 1.10
FUJIFUILM MICRODEVICES CO., LTD.
9
Bit 0
TransmitEn: Transmit Enable bit (RW- Initial value: 1b)
0
= Transmitter disabled
1
= Transmitter enabled
Setting is made to decide if the MD8412B transmitter is enabled or not. In the case of enable, the following
transmission is performed:
- Asynchronous packet
- Cycle start packet with a cycle master bit enabled
- Isochronous packet for cycle start
This bit is automatically set at "1" when a request for bus reset is received from the PHY chip.
Bit 1
ReceiveEn: Receive Enable bit (RW- Initial value: 0b)
0
= Receiver disabled
1
= Receiver enabled
Setting is made to decide if the MD8412B receiver is enabled or not. In the case of enable, the following
reception is performed:
- Synchronous packet addressed from another node to this node
- Isochronous packet of the designated channel
- Reception in snoop mode
Bit 4
LPSOn: Ink power status on bit (RW- initial value: 0b)
This bit is used to control the LPS signal supplied to the PHY chip. According to the status of the DIRECT
terminal, contents of output are different.
Bit 7
PhyIFRST: PHY-LINK I/F Reset bit (RW- Initial value: 0b)
Selection is made to determine whether the initialization of PHY-LINK I/F is performed at the time of
default or at the timing defined by P1394a.
0
= Selection is performed at the timing of Default.
1
= Selection is performed at the timing defined by P1394a.
Bit 16
CycleTimerEn: Cycle Timer Enable bit (RW- Initial value: 1b)
0
= Cycle timer disabled
1
= Cycle timer enabled
Setting is made to decide if the MD8412B cycle timer is enabled or not.
Bit 17
CycleMaster: Cycle Master bit (RW- Initial value: 1b)
0
= Receiving a cycle start packet from a node in another route, cycle timer control is effected. To be set
at "1" when this node cannot belong to an ordinary route.
1
= When this bit is "1" cycle start packet is generated each time the MD8412B cycle timer carries.
DIRECT
LPSOn
LPS output
10
0
11
1
00
0
01
Approx. 0.6 to 3.6MHz
clock (Duty 33%)
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