Nexperia

74ALVT16821

20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state

74ALVT16821

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Product data sheet

Rev. 4 — 22 January 2018

8 / 16

Symbol Parameter

Conditions

Min

Typ[1]

Max

Unit

ΔICC

additional supply current per input pin; VCC = 3 V to 3.6 V;

one input at VCC - 0.6 V;

other inputs at VCC or GND

[6]

-

0.04

0.4

mA

CI

input capacitance

VI = 0 V or VCC

-

3

-

pF

CO

output capacitance

VO = 0 V or VCC

-

9

-

pF

[1] All typical values for VCC = 2.5 V ± 0.2 V are measured at VCC = 2.5 V and Tamb = 25 °C.

All typical values for VCC = 3.3 V ± 0.3 V are measured at VCC = 3.3 V and Tamb = 25 °C.

[2] For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.

[3] Unused pins at VCC or GND.

[4] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms.

From VCC = 1.2 V to (2.5 ± 0.2) V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only.

[5] ICC with outputs disabled is measured with outputs pulled to VCC or GND.

[6] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.

[7] This is the bus hold overdrive current required to force the input to the opposite logic state.

[8] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms.

From VCC = 1,2 V to (3.3 ± 0.3) V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only.

10 Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); Tamb = -40 °C to +85 °C; for test circuit see Figure 8.

Symbol Parameter

Conditions

Min

Typ[1]

Max

Unit

VCC = 2.5 V ± 0.2 V

tPLH

LOW to HIGH propagation delay

nCP to nQn; see Figure 5

1.0

2.6

4.0

ns

tPHL

HIGH to LOW propagation delay

nCP to nQn; see Figure 5

1.0

2.7

4.4

ns

tPZH

OFF-state to HIGH propagation delay

nOE to nQn; see Figure 7

1.5

2.8

4.6

ns

tPZL

OFF-state to LOW propagation delay

nOE to nQn; see Figure 7

1.0

1.8

4.1

ns

tPHZ

HIGH to OFF-state propagation delay

nOE to nQn; see Figure 7

1.5

2.7

4.4

ns

tPLZ

LOW to OFF-state propagation delay

nOE to nQn; see Figure 7

1.0

2.1

3.3

ns

nDn to nCP; HIGH; see Figure 6

1.5

0.1

-

ns

tsu

set-up time

nDn to nCP; LOW; see Figure 6

2.0

0.5

-

ns

nDn to nCP; HIGH; see Figure 6

0.3

-0.5

-

ns

th

hold time

nDn to nCP; LOW; see Figure 6

0.5

-0.1

ns

nCP HIGH; see Figure 5

1.5

-

-

ns

tW

pulse width

nCP LOW

1.5

-

-

ns

fmax

maximum frequency

nCP; see Figure 5

150

-

-

MHz