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Gain Age Factor and EDV1 Discharge Rate Compensation (GAF/DEDV) – Address 0x7D

Discharge Rate Compensation Coefficients (DCOMP) – Address 0x7E

bq27010, bq27210

SLUS707B – APRIL 2006 – REVISED JANUARY 2007

DCFIX

Fixed discharge compensation. Normal discharge rate compensation (DCOMP register) is used if

this bit is set to 0. If this bit is set to 1, the device assumes a fixed value of 0x6C for DCOMP,

giving a discharge rate compensation gain (DCGN) of 5.08% with a compensation offset threshold

of C/2. Setting the bit to 1 frees the EEPROM location of 0x7E for use as a programmable

identification byte.

TCFIX

Fixed temperature compensation. Normal temperature compensation (TCOMP register) is used if

this bit is set to 0. If this bit is set to 1, the device assumes a fixed value of 0x46 for TCOMP, which

will increase DCGN by 25% per

°C below 12°C. Setting this bit to 1 frees the EEPROM location of

0x7F for use as a programmable identification byte.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

NAME

GAF[1]

GAF[0]

DEDV[5]

DEDV[4]

DEDV[3]

DEDV[2]

DEDV[1]

DEDV[0]

The two most significant bits in address 0x7d set the gain age factor (GAF). This factor adjusts the discharge

rate compensation with age. The GAF will cause a linear increase in the discharge rate and temperature

compensation with cycle count. GAF = 3 will cause DCGN to increase by same amount as a drop in temperature

of 16

°C below the Toff threshold programmed in TCOMP when CYCT = 85. Lower values of GAF will require

proportionally more cycle counts to reach the same level of compensation reduction. The equation for the aged

discharge compensation gain (ADCGN) is:

ADCGN = DCGN * (1 + TCGN * (CYCT/16) * GAF/32)

TCGN is the temperature compensation gain programmed in TCOMP. See the section on DCOMP for the

complete discharge rate compensation equation. There will be no gain aging of the discharge compensation if

GAF = 0. The recommended value for GAF if battery aging data is not available is GAF = 1.

The six least significant bits in address 0x7d set the EDV1 discharge rate compensation (DEDV) gain. The

EDV1 threshold is impedance-based and will be reduced from the no-load EDV1 threshold programmed in

SEDV1 as a function of load current. The EDV1 threshold is reduced linearly with AI at a rate of 8 mV per C-rate

for each DEDV count. The DEDV rate compensation is also increased at cold temperature as described in the

section on ISLC / EDVT. The actual EDV1 threshold used will be the greater of CEDV or EDVF + 32mV. The

equation for the EDV1 threshold compensation is:

CEDV = EDV1 – 8 mV * DEDV * AI / DC, where T

≥ T

off

This register is used to set the basic discharge compensation coefficients. The basic discharge gain coefficient,

DCGN, is increased at cold temperature and with age (cycle count) to achieve a combined impedance-based

discharge rate, temperature, and age compensation of available capacity. This compensation determines the

reduction in CAC from NAC and the reduction in FCAC from LMD.

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

NAME

DCGN[4]

DCGN[3]

DCGN[2]

DCGN[1]

DCGN[0]

DCOFF[2]

DCOFF[1]

DCOFF[0]

DCGN[4:0]

The discharge rate compensation gain coefficient sets the slope of the capacity compensation with

discharge current. The slope can be set in increments of 0.39% (DCGN / 256).

DCOFF[2:0] The discharge compensation offset coefficient sets the capacity offset threshold. There is no

capacity compensation reduction if the compensation falls below this threshold. Table 3 lists shows

the discharge compensation threshold is set in multiples of C/8. (A 1C-rate current is the current

that equals the design capacity, or AI = ILMD * 256.)

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