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UPC4081C Datasheet(PDF) 3 Page - Renesas Technology Corp |
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UPC4081C Datasheet(HTML) 3 Page - Renesas Technology Corp |
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3 / 14 page ![]() © 1987 BIPOLAR ANALOG INTEGRATED CIRCUIT µµµµPC4081 J-FET INPUT OPERATIONAL AMPLIFIER DATA SHEET Document No. G15343EJ3V0DS00 (3rd edition) (Previous No. IC-1974) Date Published February 2001 NS CP(K) Printed in Japan The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. The mark 5 shows major revised points. DESCRIPTION The µPC4081 is a single operational amplifier incorporating well matched ion implant P-channel J-FET on the same chip with standard bipolar transistors. The key features of this op amp is very low input bias current and high slew rate ten times faster than conventional general purpose op amps. By these features µPC4081 is excellent choice for wide variety of applications including integrator, active filter, pulse amp etc. FEATURES • Low noise: en = 25 nV/ Hz (TYP.) • Very low input bias and offset currents • Output short circuit protection • High input impedance...J-FET Input stage • Internal frequency compensation • High slew rate...13 V/ µs (TYP.) ORDERING INFORMATION Part Number Package µPC4081C 8-pin plastic DIP (7.62 mm (300)) µPC4081G2 8-pin plastic SOP (5.72 mm (225)) EQUIVALENT CIRCUIT PIN CONFIGURATION (Top View) PC4081C, 4081G2 1 2 3 4 8 7 6 5 NC V+ OUT OFFSET NULL + _ OFFSET NULL II IN V µ _ Remark NC : No Connection R1 R8 R9 R6 D1 R7 R10 R11 D2 Q15 R4 R2 R5 R3 II IN (2) Q1 Q2 Q8 Q16 Q9 Q10 Q12 Q13 Q5 Q14 Q3 Q4 Q11 Q6 Q7 C1 OFFSET NULL OFFSET NULL OUT V – V + (3) (1) (5) (6) (4) (7) |
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