Data Sheet U13594EJ2V1DS00

17

µPD6P4B

AC Characteristics (TA = –40 to +85

°C, VDD = 2.2 to 3.6 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Instruction execution time tCY

15.9

27

µs

VDD = 2.7 to 3.6 VNote 1

7.9

27

µs

KI, S0, S1 high-level width

tH

10

µs

When canceling Standby mode

HALT mode

10

µs

STOP mode

Note 2

µs

RESET low-level width

tRSL

10

µs

Notes 1. When using at fX = 4 MHz or higher, it is necessary to design the application circuit so that the RESET

pin goes low when the supply voltage is less than 2.7 V.

2. 10 + 286/fX + oscillation growth time

Remark tCY = 64/fX (fX: System clock oscillator frequency)

POC CircuitNote 1 (TA = –20 to +70

°C)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

POC-detected voltageNote 2

VPOC

1.8

2.0

2.2

V

POC circuit current

IPOC

1.2

1.5

µA

Notes 1. Operates effectively under the conditions of fX = 2.4 to 4 MHz.

2. Refers to the voltage with which the POC circuit cancels an internal reset. If VPOC < VDD, the internal

reset is canceled.

From the time of VPOC

≥ VDD until the internal reset takes effect, lag of up to 1 ms occurs. When the

period of VPOC

≥ VDD lasts less than 1 ms, the internal reset may not take effect.

System Clock Oscillator Characteristics (TA = –40 to +85

°C, VDD = 2.2 to 3.6 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Oscillator frequency

fX

2.4

3.64

4.0

MHz

(ceramic resonator)

Note

2.4

3.64

8.0

MHz

Note When using at fX = 4 MHz or higher, it is necessary to design the application circuit so that the RESET

pin goes low when the supply voltage is less than 2.7 V.

An external circuit example

XIN

XOUT

C1

C2

Rd