Nexperia

74ALVC374

Octal D-type flip-flop; positive-edge trigger; 3-state

ten is the same as tPZH and tPZL.

tdis is the same as tPHZ and tPLZ.

[3] CPD is used to determine the dynamic power dissipation (PD in μW).

PD = CPD × VCC 2 × fi × N + Σ(CL × VCC 2 × fo) where:

fi = input frequency in MHz; fo = output frequency in MHz

CL = output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(CL × VCC 2 × fo) = sum of the outputs

10.1. Waveforms and test circuit

mna894

CP input

Qn output

tPHL

tPLH

tW

1/fmax

VM

VOH

VI

GND

VOL

VM

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage levels that occur with the output load.

Fig. 7. Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum frequency

mna644

tPLZ

tPHZ

outputs

disabled

outputs

enabled

VY

VX

outputs

enabled

output

LOW-to-OFF

OFF-to-LOW

output

HIGH-to-OFF

OFF-to-HIGH

OE input

VI

VOL

VOH

VCC

VM

GND

GND

tPZL

tPZH

VM

VM

Measurement points are given in Table 8.

VOL and VOH are the typical output voltage drops that occur with the output load.

Fig. 8. Enable and disable times

74ALVC374

All information provided in this document is subject to legal disclaimers.

© Nexperia B.V. 2021. All rights reserved

Product data sheet

Rev. 3 — 30 April 2021

7 / 15