CY2273A
7
Switching Characteristics for CY2273A-1, CY2273A-2[8]Over the Operating Range
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
t1
All
Output Duty Cycle[9, 10] t1 = t1A ÷ t1B
45
50
55
%
t2
CPUCLK
CPU Clock Rising and
Falling Edge Rate[10]
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.75
4.0
V/ns
t2
SDRAM, PCI,
REF0, USB
SDRAM, PCI, REF0
Clock Rising and Fall-
ing Edge Rate[10]
Between 0.4V and 2.4V
0.85
4.0
V/ns
t2
AGP (-2 only)
AGP Rising and Falling
Edge Rate
Between 0.4V and 2.4V
0.85
4.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
Between 0.4V and 2.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.67
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
Between 2.4V and 0.4V, VDDCPU = 3.3V
0.4
0.5
2.13
2.67
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V, VDDCPU = 2.5V
Measured at 1.5V, VDDCPU = 3.3V
100
250
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1.0
3.0
5.5
ns
t7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew[10]
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
650
ps
t8
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
500
ps
t9
PCICLK,
AGP (-2 only)
PCICLK-AGP Clock
Skew (-2 only)
Measured at 1.5V
500
ps
t10
CPUCLK,
SDRAM
Cycle-Cycle Clock
Jitter[10]
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
250
ps
t10
PCICLK,
AGP (-2 only)
Cycle-Cycle Clock
Jitter[10]
Measured at 1.5V
500
ps
t11
CPUCLK,
PCICLK,
AGP (-2 only),
SDRAM
Power-up Time
CPU, PCI, AGP, and SDRAM clock sta-
bilization from power-up
3
ms
Notes:
8.
All parameters specified with loaded outputs.
9.
Duty cycle is measured at 1.5V when VDD = 3.3V. When VDDCPU = 2.5V, CPUCLK duty cycle is measured at 1.25V.
10. Measured at CPU=66.6 MHz, SDRAM=66.6 MHz, PCI=33.3 MHz, AGP=66.6 MHz.
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