CY2273A
9
Switching Characteristics for CY2273A-4[8]Over the Operating Range
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
t1
All
Output Duty Cycle[9]
t1 = t1A ÷ t1B
45
50
55
%
t2
CPUCLK
CPU Clock Rising and
Falling Edge Rate
Between 0.4V and 2.0V, VDDCPU = 2.5V 0.75
1.0
4.0
V/ns
t2
SDRAM
PCI, REF0,
USB
SDRAM, PCI, REF0,
USB Clock Rising and
Falling Edge Rate
Between 0.4V and 2.4V
0.85
1.0
4.0
V/ns
t3
CPUCLK
CPU Clock Rise Time
Between 0.4V and 2.0V, VDDCPU = 2.5V
0.4
2.13
ns
t4
CPUCLK
CPU Clock Fall Time
Between 2.0V and 0.4V, VDDCPU = 2.5V
0.4
2.13
ns
t5
CPUCLK
CPU-CPU Clock Skew
Measured at 1.25V
100
250
ps
t6
CPUCLK,
PCICLK
CPU-PCI Clock Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
1200
ps
t7
CPUCLK,
SDRAM
CPU-SDRAM Clock
Skew
Measured at 1.25V for 2.5V clocks, and
at 1.5V for 3.3V clocks
650
ps
t8
PCICLK,
PCICLK
PCI-PCI Clock Skew
Measured at 1.5V
500
ps
t10
CPUCLK,
Cycle-Cycle Clock Jitter
Measured at 1.25V, VDDCPU = 2.5V
650
ps
t10
SDRAM
Cycle-Cycle Clock Jitter
Measured at 1.5V
650
ps
t10
PCICLK
Cycle-Cycle Clock Jitter
Measured at 1.5V
1200
ps
t11
CPUCLK,
PCICLK,
SDRAM
Power-up Time
CPU, PCI, AGP, and SDRAM clock sta-
bilization from power-up
3
ms
Timing Requirement for the I2C Bus
Parameter
Description
Min.
Max.
Unit
t12
SCLK Clock Frequency
0
100
kHz
t13
Time the bus must be free before a new transmission can start
4.7
µs
t14
Hold time start condition. After this period the first clock pulse is generated.
4
µs
t15
The Low period of the clock.
4.7
µs
t16
The High period of the clock.
4
µs
t17
Set-up time for start condition. (Only relevant for a repeated start condition.)
4.7
µs
t18
Hold time DATA
for CBUS compatible masters.
for I2C devices
5
0
µs
t19
DATA input set-up time
250
ns
t20
Rise time of both SDATA and SCLK inputs
1
µs
t21
Fall time of both SDATA and SCLK inputs
300
ns
t22
Se-up time for stop condition
4.0
µs
Switching Waveforms
Duty Cycle Timing
t1A
t1B
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