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UPD78P324LP Datasheet(PDF) 66 Page - Renesas Technology Corp |
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UPD78P324LP Datasheet(HTML) 66 Page - Renesas Technology Corp |
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66 / 82 page  µPD78P324, 78P324(A) 64 PROM Write Mode Timing Cautions 1. Ensure to apply VDDP before VPP, and disconnect it after VPP. 2. Ensure that VPP does not exceed +13.5 V even when the overshoot is included. 3. Taking out or putting in while +12.5 V is applied to VPP may cause adverse effects on the reliability. PROM Read Mode Timing Notes 1. To read within the range of tACC, please make sure that the delay time from CE’s falling edge of the OE input is up to tACC-tOE. 2. tDF refers to the time when either OE or CE became VIH first. A0-A16 D0-D7 VPP VDDP VDDP + 1.5 VDDP VIH VIL VIH VIL VIH VIL VPP VDDP CE PGM OE Hi-Z Program Program verify tDS tAS tVPS tVDS tCES Data output Data input Hi-Z tAH Hi-Z tDH tDF tPW tOES tOE Note 1 tOE Note 2 A0-A16 CE OE D0-D7 Vailed address Hi-Z tACC Data output Hi-Z tOH tDF Note 1 |
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