MP1909

– 30V, HIGH-FREQUENCY HALF-BRIDGE GATE DRIVER

MP1909 Rev. 1.0

www.MonolithicPower.com

5

7/10/2020

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© 2020 MPS. All Rights Reserved.

ELECTRICAL CHARACTERISTICS (continued)

VCC = VBST - VSW = 12V, VEN = 3.3V, VPWM = 3.3V, no load at DRVH and DRVL, TJ = -40°C to +125°C

(7), typical value is tested at TJ = 25°C, unless otherwise noted.

Parameter

Symbol

Condition

Min

Typ

Max

Units

Output resistance, sinking current

ROLL

VPWM = 3.3V, VCC = 5V

1

Ω

VPWM = 3.3V, VCC = 12V

0.6

Ω

IOLL (8)

VPWM = 3.3V, VCC = 12V

4

A

Output resistance, unbiased

ROUL

VCC = GND

250

k

Ω

Floating Gate Driver

Output resistance, source current

ROHH

VPWM = 3.3V, VBST - VSW = 5V

4

Ω

VPWM = 3.3V, VBST - VSW = 12V

2

Ω

Output resistance, sink current

ROLH

VPWM = 0V, VBST - VSW = 5V

1.2

Ω

VPWM = 0V, VBST - VSW = 12V

0.6

Ω

Output resistance, unbiased

ROUH

VBST - VSW = 0V

250

k

Ω

Switching Specifications (Low-Side Gate Driver)

Turn-off propagation delay,

PWM rising to DRVL falling

tDLRF

30

ns

Turn-on propagation delay,

PWM falling to DRVL rising

tDLFR

110

ns

DRVL rise time (8)

tDRVL_R

CL = 1nF

10

ns

DRVL fall time (8)

tDRVL_F

CL = 1nF

6

ns

Switching Specifications (Floating Gate Driver)

Turn-off propagation delay,

PWM falling to DRVH falling

tDHFF

40

ns

Turn-on propagation delay,

PWM rising to DRVH rising

tDHRR

80

ns

DRVH rise time (8)

tDRVH_R

CL = 1nF

10

ns

DRVH fall time (8)

tDRVH_F

CL = 1nF

6

ns

Switching Specifications (Matching)

Minimum input pulse width that

changes the output (8)

tPW

50

ns

Thermal shutdown (8)

TSTD

150

°C

Thermal hysteresis (8)

TSTD_HYS

20

°C

Notes:

7) Not tested in production. Guaranteed by over-temperature correlation.

8) Guaranteed by design and engineering sample characterization.

TIMING DIAGRAM

tDHRR

tDHFF

Input

(PWM)

Output

(DRVH)

Input

(PWM)

Output

(DRVL)

tDLFR

tDLRF