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M24C64-FMB5TG/P Datasheet(PDF) 10 Page - STMicroelectronics |
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M24C64-FMB5TG/P Datasheet(HTML) 10 Page - STMicroelectronics |
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10 / 34 page ![]() Signal description M24128, M24C64, M24C32 10/34 Figure 5. I2C bus protocol Table 3. Device select code Device Type Identifier(1) 1. The most significant bit, b7, is sent first. Chip Enable Address(2) 2. E0, E1 and E2 are compared against the respective external pins on the memory device. RW b7 b6 b5 b4 b3 b2 b1 b0 Device Select Code 1 0 1 0 E2 E1 E0 RW Table 4. Address most significant byte b15 b14 b13 b12 b11 b10 b9 b8 Table 5. Address least significant byte b7 b6 b5 b4 b3 b2 b1 b0 SCL SDA SCL SDA SDA START Condition SDA Input SDA Change AI00792B STOP Condition 1 23 7 89 MSB ACK START Condition SCL 1 23 7 89 MSB ACK STOP Condition |
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