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PHN203

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Product data sheet

Rev. 05 — 27 April 2010

2 of 13

Nexperia

PHN203

Dual N-channel TrenchMOS logic level FET

2.

Pinning information

3.

Ordering information

4.

Limiting values

[1]

Single device conducting.

Table 2.

Pinning information

Pin

Symbol

Description

Simplified outline

Graphic symbol

1S1

source1

SOT96-1 (SO8)

2

G1

gate1

3S2

source2

4

G2

gate2

5D2

drain2

6D2

drain2

7D1

drain1

8D1

drain1

4

5

1

8

D1

mbk725

G1

S1

D1

D2

G2

S2

D2

Table 3.

Ordering information

Type number

Package

Name

Description

Version

PHN203

SO8

plastic small outline package; 8 leads; body width 3.9 mm

SOT96-1

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

VDS

drain-source voltage

Tj ≥ 25 °C; Tj ≤ 150 °C

--30

V

VDGR

drain-gate voltage

Tj ≤ 150 °C; Tj ≥ 25 °C; RGS =20kΩ

--30

V

VGS

gate-source voltage

-20

-

20

V

ID

drain current

Tamb = 70 °C; pulsed; see Figure 1

[1]

--5

A

Tamb = 25 °C; pulsed; see Figure 1;

see Figure 3

[1]

--6.3

A

IDM

peak drain current

tp ≤ 10 µs; pulsed; Tamb =25°C;

see Figure 3

[1]

--18

A

Ptot

total power dissipation

Tamb = 25 °C; pulsed; see Figure 2

[1]

--2

W

Tstg

storage temperature

-55

-

150

°C

Tj

junction temperature

-55

-

150

°C

Source-drain diode

IS

source current

Tamb = 25 °C; pulsed

[1]

--2

A

ISM

peak source current

tp ≤ 10 µs; pulsed; Tamb =25°C

[1]

--4.1

A

Avalanche ruggedness

EDS(AL)S

non-repetitive

drain-source

avalanche energy

VGS =10V; Tj(init) =25°C; ID =8.7 A;

Vsup ≤ 30 V; unclamped; tp = 0.2 ms;

RGS =50 Ω

-

-

37.8

mJ