UPD30102 datasheet(13/114 Pages) RENESAS

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µPD30102

Preliminary Data Sheet

1. PIN FUNCTIONS

Remark # indicates active low.

1.1 Pin Functions

(1) System bus interface signals

(1/2)

Signal Name

I/O

Function

ADD (0:25)

This is a 25-bit address bus. Used to specify addresses of the VR4102, DRAM, ROM,

LCD, and system bus (ISA).

DATA (0:15)

I/O

This is a 16-bit data bus. Used to transfer data from the VR4102 to DRAM, ROM, LCD,

and system bus, and vice versa.

DATA (16:31)/

I/O

This function differs depending on how the DBUS32 pin is set.

GPIO (16:31)

It is the high-order 16 bits of the 32-bit data bus.

This bus is used for transmitting and receiving data between the VR4102 and the DRAM

and ROM.

It is a general-purpose I/O (GPIO) port.

LCDCS#

This is the LCD chip select signal. This signal is active when the VR4102 is performing

LCD access using the ADD/DATA bus.

RD#

Active when the VR4102 is reading data from the LCD, RAM, or ROM.

WR#

Active when the VR4102 is writing data to the LCD, RAM, or ROM.

LCDRDY

This is the LCD ready signal. Set this signal as active when the LCD controller is ready

to be accessed from the VR4102.

ROMCS (0:3)#

This is the ROM chip select signal. It is used to select a ROM to be accessed from

among up to four connected ROM units.

UUCAS#/

This function differs depending on how the DBUS32 pin is set.

MRAS3#

UUCAS#

This signal is active when a valid column address is output via the ADD bus during

access of DATA (24:31) in the 32-bit data bus.

MRAS3#

This is the DRAM’s RAS signal. Up to four DRAM units can be connected, and this

signal is active when a valid row address is output via the ADD bus for the DRAM

connected to the high-order address.

ULCAS#/

This function differs depending on how the DBUS32 pin is set.

MRAS2#

ULCAS#

This signal is active when a valid column address is output via the ADD bus during

access of DATA (16:23) in the 32-bit data bus.

MRAS2#

This is the DRAM’s RAS signal. This signal is active when a valid row address is output

via the ADD bus for the DRAM connected to the next-highest address after the highest

high-order address.

MRAS (0:1)#

This is the DRAM’s RAS-only signal.

UCAS#

This is the DRAM’s CAS signal. This signal is active when a valid column address

is output via the ADD bus during access of DATA (8:15) in the DRAM.

UPD30102 Datasheet(PDF) 13 Page - Renesas Technology Corp

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