MB90347CE datasheet(67/85 Pages) FUJITSU

67 / 85 page

MB90340E Series

(13) I2C Timing

(TA

= –40°C to +105°C, VCC = 5.0 V ± 10%, VSS = 0.0 V)

*1: For use at over 100 kHz, set the machine clock to at least 6 MHz.

*2: R,C: Pull-up resistor and load capacitor of the SCL and SDA lines.

*3: The maximum tHDDAT meets the requirement that it does not extend the “L” width (tLOW) of the SCL signal.

*4: A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement

tSUDAT

≥ 250 ns must then be met.

Parameter

Symbol

Condition

Standard-mode

Fast-mode*1

Unit

Min

Max

Min

Max

SCL clock frequency

fSCL

= 1.7 kΩ,

= 50 pF*2

100

400

kHz

Hold time (repeated) START condition

SDA

↓ → SCL ↓

tHDSTA

4.0

⎯

0.6

⎯µs

“L” width of the SCL clock

tLOW

4.7

⎯

1.3

⎯µs

“H” width of the SCL clock

tHIGH

4.0

⎯

0.6

⎯µs

Set-up time (repeated) START condition

SCL

↑ → SDA ↓

tSUSTA

4.7

⎯

0.6

⎯µs

Data hold time

SCL

↓ → SDA ↓ ↑

tHDDAT

3.45*3

00.9*4

µs

Data set-up time

SDA

↓ ↑ → SCL ↑

tSUDAT

250

⎯

100

⎯

Set-up time for STOP condition

SCL

↑ → SDA ↑

tSUSTO

4.0

⎯

0.6

⎯µs

Bus free time between a STOP and START

condition

tBUS

4.7

⎯

1.3

⎯µs

SDA

SCL

tLOW

tSUDAT

tHDSTA

tBUS

tHDSTA

tHDDAT

tHIGH

tSUSTA

tSUSTO

MB90347CE Datasheet(PDF) 67 Page - fujitsu semiconductor

MB90347CE Datasheet(HTML) 67 Page - fujitsu semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85

Datasheet Download

Link URL