UPD98408 datasheet(13/38 Pages) RENESAS

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Data Sheet S12313EJ3V0DS

µµµµPD98408

1.3 UTOPIA Interface

Pin Name

Pin No.

I/O

Active

Level

Function

RxDATA0-

RxDATA7

69, 68, 66, 65,

63, 62, 60, 59

Tristate

−

8-bit data bus used for receive data output to the ATM layer

device. Data is output in sync with the positive-going edge of

RxCLK.

RxCLK

−

Input pin of the clock for receive data transfer to the ATM layer

device.(Max. 40 MHz)

RxSOC

Tristate

Receive cell start address signal output, which outputs the

signal for informing the ATM layer device of the start byte

position of the receive cell. The start byte position is that

position where RxSOC = 1.

RxENB_B

RxDATA0-RxDATA7 and RxSOC output enable signal input.

When 0 is input, outputs RxDATA0-RxDATA7 and RxSOC are

enabled.

RxADDR0-

RxADDR4

80, 77, 76, 74,

−

Input pins for the signal indicating the address of the

µPD98408.

RxCLAV

Tristate

Cell receive available signal output. Becomes 1 when the

µPD98408 has an output cell.

TxDATA0-

TxDATA7

97, 96, 94, 93,

91, 90, 88, 87

−

8-bit data bus used for transmit data input to the ATM layer

device. Data is input in sync with the positive-going edge of

TxCLK.

TxCLK

−

Input pin of the clock for the transmit data transfer to the ATM

layer device. (Max. 40 MHz)

TxSOC

109

Transmit cell start address signal input, which inputs the signal

indicating the start byte position of the transmit cell input from

the ATM layer device. The start byte position is that position

where TxSOC = 1.

TxENB_B

112

Transmit enable signal input, which inputs a signal indicating

that the ATM layer device is outputting valid transmit data at

TxDATA0-TxDATA7. 0 for enable and 1 for disable.

TxADDR0-

TxADDR4

108, 107, 103,

102, 101

−

Input pins of the signal indicating the address of the

µPD98408

which transmits data

TxCLAV

111

Tristate

Cell transmit available signal output. Goes to 1 when the

µPD98408 is ready to receive a cell.

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