UPD98412 datasheet(39/66 Pages) RENESAS

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Data Sheet S14237EJ2V0DS00

µµµµPD98412

Table 1-7. Transmit Interface Signals (1/2)

Symbol

Pin No.

I/O

Function

TXADDR0A3 -

TXADDR0A0

97, 207, 98, 402

Multi-PHY select address of transmit interface 0, group A.

TXADDR0A3 is the MSB.

TXADDR0B3 -

TXADDR0B0

216, 108, 409, 317

Multi-PHY select address of transmit interface 0, group B.

TXADDR0B3 is the MSB.

TXENB0A_B

403

Transfer enable signal of transmit interface 0, group A.

This signal informs a PHY layer device that the

µPD98412 outputs

data in the current clock cycle.

TXENB0B_B

218

Transfer enable signal of transmit interface 0, group B.

This signal informs a PHY layer device that the

µPD98412 outputs

data in the current clock cycle.

TXCLAV0A

208

Cell transfer enable signal of transmit interface 0, group A.

This pin inputs a signal that indicates that the

µPD98412 is ready

to receive the next cell after transfer of the current cell is

completed.

TXCLAV0B

109

Cell transfer enable signal of transmit interface 0, group B.

This pin inputs a signal that indicates that the

µPD98412 is ready

to receive the next cell after transfer of the current cell is

completed.

TXDATA015 -

TXDATA000

572, 411, 319, 219, 111, 412,

320, 220, 310, 209, 100, 404,

311, 210, 102, 211

Cell data output of transmit interface 0.

Cell data is output to a PHY layer device in 16-bit units.

The

µPD98412 outputs the data at the rising edge of UCLK0.

TXDATA015 is the MSB.

(3-state buffer)

TXSOC0

Cell transfer start signal of transmit interface 0.

This signal is output to a PHY layer device in synchronization with

the first byte of cell data.

(3-state buffer)

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