PMR400UN

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© NXP B.V. 2012. All rights reserved.

Product data sheet

Rev. 2 — 2 February 2012

2 of 13

NXP Semiconductors

PMR400UN

N-channel TrenchMOS ultra low level FET

3.

Ordering information

4.

Marking

5.

Limiting values

Table 3.

Ordering information

Type number

Package

Name

Description

Version

PMR400UN

SC-75

plastic surface-mounted package; 3 leads

SOT416

Table 4.

Marking codes

Type number

Marking code

PMR400UN

R7

Table 5.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

Parameter

Conditions

Min

Max

Unit

VDS

drain-source voltage

Tj ≥ 25 °C; Tj ≤ 150 °C

-

30

V

VDGR

drain-gate voltage

Tj ≥ 25 °C; Tj ≤ 150 °C; RGS =20kΩ

-30

V

VGS

gate-source voltage

-8

8

V

ID

drain current

Tsp =25 °C; VGS = 4.5 V

-

0.8

A

Tsp = 100 °C; VGS = 4.5 V

-

0.51

A

IDM

peak drain current

Tsp = 25 °C; pulsed; tp ≤ 10 µs

-

1.61

A

Ptot

total power dissipation

Tsp = 25 °C

-

0.53

W

Tstg

storage temperature

-55

150

°C

Tj

junction temperature

-55

150

°C

Source-drain diode

IS

source current

Tsp = 25 °C

-

0.44

A

ISM

peak source current

Tsp = 25 °C; pulsed; tp ≤ 10 µs

-

0.88

A