MAS9560 datasheet(20/25 Pages) MAS

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DA9560.001

20 January, 2005

0x02[1:0]

R/W

Power Mode [1:0]

00 Zero Power Mode

01 Standby Mode

11 Operating Mode

10 Undefined (do not use)

2S Control Register

0x03

R/W

0x00

0x03[7:5]

Unused

POL

0x03[4]

R/W

Invert Word Strobe Input (WSI) polarity:

POL = 0 -> Left Channel @ WSI = 0

POL = 1 -> Right Channel @ WSI = 0

DEL

0x03[3]

R/W

Delayed Bit: 1 = Delay, 0 = no Delay

0x03[2:0]

R/W

000

Sample Rate [2:0]

000, 110 or 111: sample rate defined by

WSI, DAC data not filtered.

SR[2:0] LP Filter –3dB frequency:

001

fCLI/128 * 0.65

010

fCLI/64 * 0.65

011

fCLI/32 * 0.65

100

fCLI/16 * 0.65

101 fCLI/8 * 0.65

fCLI refers to I2S clock (CLI pin) frequency.

The above mentioned SR[2:0] register bits

allow filtering the DAC output by setting the

filter frequency.

An example: DAC data is given in stereo

mode as 16 bit data. Sampling frequency

WSI = 8 kHz, and CLI frequency is 2*16*8

kHz (2 channels, 16 bit each, 8 kHz

sampling freq). Highest signal frequency is

4 kHz (according to Nyqvist theorem), and

thus low pass filtering can be set to 4 kHz.

Now SR[2:0] = 011, which sets –3 dB

frequency to 5.2 kHz (= 2*16*8 kHz /

32*0.65).

Left Headphone

Volume Register

0x04

R/W

0x04[7:5]

Unused

LHV[4:0] Left Headphone volume gain

LHV

0x04[4:0]

R/W

00000

00001

...

11001...11111

Mute

-30 dB

in steps of 1.5 dB

6 dB

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