WM8971L datasheet(48/61 Pages) WOLFSON

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WM8971L

Production Data

PD Rev 4.1 August 2005

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

8:7

VMIDSEL

Vmid divider enable and select

00 – Vmid disabled (for OFF mode)

01 – 50k

Ω divider enabled (for

playback/record)

10 – 500k

Ω divider enabled (for low-power

standby)

11 – 5k

Ω divider enabled (for fast start-up)

VREF

VREF (necessary for all other functions)

Power down = 0

Power up = 1

AINL

Analogue in PGA Left

Power down = 0

Power up = 1

AINR

Analogue in PGA Right

Power down = 0

Power up = 1

ADCL

ADC Left

Power down = 0

Power up = 1

ADCR

ADC Right

Power down = 0

Power up = 1

R25 (19h)

Power

Management

(1)

MICB

MICBIAS

Power down = 0

Power up = 1

DACL

DAC Left

Power down = 0

Power up = 1

DACR

DAC Right

Power down = 0

Power up = 1

LOUT1

LOUT1 Output Buffer*

Power down = 0

Power up = 1

ROUT1

ROUT1 Output Buffer*

Power down = 0

Power up = 1

LOUT2

LOUT2 Output Buffer*

Power down = 0

Power up = 1

ROUT2

ROUT2 Output Buffer*

Power down = 0

Power up = 1

R26 (1Ah)

Power

Management

(2)

MONO

MONOOUT Output Buffer and Mono Mixer

Power down = 0

Power up = 1

* The left mixer is enabled when LOUT1=1 or LOUT2=1. The right mixer is enabled when

ROUT1=1 or ROUT2=1.

Table 39 Power Management

WM8971L Datasheet(PDF) 48 Page - Wolfson Microelectronics plc

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