G52197-0, Rev. 4.0

© VITESSE SEMICONDUCTOR CORPORATION

Page 3

8/19/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC6250

1Gb/s 16-Channel

Drive-Side Deskew IC

Functional Description

The VSC6250 is a 1Gb/s 16-channel drive-path deskew IC designed for deskewing differences in path

delay between multiple DUTs in a high-speed memory test system. The VSC6250 can be used as two indepen-

dent 1:8 fanout and deskew sections or as a single 1:16 fanout and deskew. When used as two 1:8 deskews,

input signals are applied to inputs DINA and DINB. When used as a single 1:16 deskew, the input is applied to

input DIN.

The VSC6250 is designed to operate with a conventional 500MHz timing generator which outputs format-

ted pulses to the VSC6250 deskew IC. See Figure 1. The waveform at the input of the VSC6250 is the same as

that presented to the DUT pin. In a memory tester, such a 500MHz timing generator IC may be designed:

• Using one edge to output a single 500Mb/s data stream

• Using two edges to output a single 500Mb/s data stream preceded its complement

• Using three edges to output a single data stream at 500Mb/s surrounded by its complement

• Using two edges to output two interleaved 500Mb/s data streams for an aggregate bandwidth of 1Gb/s.

Formatting is performed inside the timing generator IC. An example interface between the timing generator

IC and the deskew is shown in Figure 1. This configuration is capable of supporting the four different data out-

put choices, with appropriate design of the formatting logic.

The VSC6250 can handle pulses with a data rate up to 1Gb/s or a pulse repetition rate up to 2ns. A timing

diagram for the VSC6250 is shown in Figure 2.

Figure 1: VSC6250 Interface to Timing Generator IC

Figure 2: VSC6250 AC Timing Diagram

S

Format

Logic

Timeset/Dataset

RAM

Timing Generator

VSC6250

R

S

R

S

R

DINx

DOUTx