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RT5133AWSC Datasheet(PDF) 22 Page - Richtek Technology Corporation |
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RT5133AWSC Datasheet(HTML) 22 Page - Richtek Technology Corporation |
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22 / 41 page ![]() RT5133A Copyright © 2022 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. www.richtek.com DS5133A-00 March 2022 22 Address Reg Name Bit Bit Name Default Type Description 0x0B GPO_CTRL 7 GPO1_EN 0 RW Enable control of GPO1 0 : Disable (default) 1 : Enable 6 GPO2_EN 0 RW Enable control of GPO2 0 : Disable (default) 1 : Enable 5 GPO3_EN 0 RW Enable control of GPO3 0 : Disable (default) 1 : Enable 4 Reserved 0 RW 3 GPO1_TX 0 RW GPO1 output signal 0 : Low (default) 1 : High 2 GPO2_TX 0 RW GPO2 output signal 0 : Low (default) 1 : High 1 GPO3_TX 0 RW GPO3 output signal 0 : Low (default) 1 : High 0 Reserved 0 RW Reserved 0x10 IRQ_MASK (IRQ Source Indicator Mask) 7 VDDAUV_EVT 0 WC VDDAUV Event 0 : No event 1 : Event occurred 6 VREF_EVT 0 WC BASE VREF Event 0 : No event 1 : Event occurred 5:3 Reserved 000 WC 2 OTP2_EVT 0 WC OTP2 Event 0 : No event 1 : Event occurred 1 OTP1_EVT 0 WC OTP1 Event 0 : No event 1 : Event occurred 0 OTP0_EVT 0 WC OTP0 Event 0 : No event 1 : Event occurred |
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