CS51311GD14 datasheet(5/21 Pages) ONSEMI

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CS51311

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ELECTRICAL CHARACTERISTICS (continued) (0°C < TA < 70°C; 0°C < TJ < 125°C; 9.0 V < VCC < 14 V;

2.0 V DAC Code (VID4 = VID3 = VID2 = VID1 = 0, VID0 = 1.0) CGATE(H) = CGATE(L) = 3.3 nF, COFF = 390 pF; unless otherwise specified.)

Characteristic

Unit

Max

Typ

Min

Test Conditions

Power Good Output

PWRGD Sink Current

VFB = 1.7 V, VPWRGD = 1.0 V

0.5

4.0

PWRGD Upper Threshold

% of Nominal DAC Code

5.0

8.5

PWRGD Lower Threshold

% of Nominal DAC Code

−12

−8.5

−5.0

PWRGD Output Low Voltage

VFB = 1.7 V, IPWRGD = 500 μA

−

0.2

0.3

General Electrical Specifications

VCC Monitor Start Threshold

−

7.9

8.4

8.9

VCC Monitor Stop Threshold

−

7.6

8.1

8.6

Hysteresis

Start−Stop

0.15

0.3

0.6

VCC Supply Current

No Load on GATE(H), GATE(L)

−

PACKAGE PIN DESCRIPTION

PACKAGE PIN #

PIN SYMBOL

FUNCTION

SO−14

1, 2, 3, 4, 5

VID0−VID4

Voltage ID DAC inputs. These pins are internally pulled up to 5.65 V if left

open. VID4 selects the DAC range. When VID4 is high (logic one), the Error

Amp reference range is 2.125 V to 3.525 V with 100 mV increments. When

VID4 is low (logic zero), the Error Amp reference voltage is 1.325 V to 2.075 V

with 50 mV increments.

VFB

Error amp inverting input, PWM comparator non−inverting input, current limit

comparator non−inverting input, PWRGD comparator input.

VOUT

Current limit comparator inverting input.

VCC

Input power supply pin for the internal circuitry. Decouple with filter capacitor to

GND.

GATE(H)

High side switch FET driver pin.

GND

Ground pin.

GATE(L)

Low side synchronous FET driver pin.

PWRGD

Power Good Output. Open collector output drives low when VFB is out of regu-

lation.

COFF

Off−Time Capacitor pin. A capacitor from this pin to GND sets the off time for

the regulator.

COMP

Error amp output. PWM comparator inverting input. A capacitor on this pin pro-

vides error amp compensation.

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